Module Definition
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Module : tlul_rsp_intg_gen
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 91.67 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_adapter.u_rsp_gen 100.00 100.00 100.00
tb.dut.u_reg.u_rsp_intg_gen 100.00 100.00 100.00
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_adapter.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.96 98.57 96.67 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.31 100.00 97.23 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.44 100.00 97.78 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter.u_rsp_gen

SCORELINE
100.00 100.00
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL6583.33
CONT_ASSIGN32100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 0 1
43 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Module : tlul_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1809 1809 0 0
PayLoadWidthCheck 1809 1809 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1809 1809 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T10 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1809 1809 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T6 3 3 0 0
T10 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN3200
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 excluded
Exclude Annotation: [UNR] EnableRspIntgGen = '0'
43 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rsp_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 493 493 0 0
PayLoadWidthCheck 493 493 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 493 493 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 493 493 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_reg.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 658 658 0 0
PayLoadWidthCheck 658 658 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658 658 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 658 658 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN3200
CONT_ASSIGN4300
ALWAYS4733100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
32 excluded
Exclude Annotation: [UNR] EnableRspIntgGen = '0'
43 excluded
Exclude Annotation: [UNR] EnableRspIntgGen = '0'
47 1 1
48 1 1
49 1 1
53 1 1


Assert Coverage for Instance : tb.dut.u_reg.u_reg_if.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 658 658 0 0
PayLoadWidthCheck 658 658 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 658 658 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 658 658 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

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