Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43183731	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

41159077

1

T1

192264

T2

949243

T3

103698

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	40002753	1			T1	174483		T2	895803		T3	107364
values[0x0]	20787240	1			T1	94977		T2	499350		T3	52663
values[0x1]	23552815	1			T1	106429		T2	548283		T3	60520

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33244738	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51098070

1

T1

233076

T2

117368

T3

130039

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	269875	1			T2	7485		T3	894		T5	140
valid_sources[0x01]	261877	1			T2	7648		T3	807		T5	170
valid_sources[0x02]	282013	1			T2	7361		T3	833		T5	217
valid_sources[0x03]	291538	1			T2	7722		T3	791		T5	181
valid_sources[0x04]	267766	1			T2	7558		T3	851		T5	160
valid_sources[0x05]	331246	1			T2	7800		T3	814		T5	216
valid_sources[0x06]	429595	1			T2	7489		T3	842		T5	217
valid_sources[0x07]	304017	1			T2	7485		T3	817		T5	190
valid_sources[0x08]	279212	1			T2	7698		T3	781		T5	193
valid_sources[0x09]	266667	1			T2	7492		T3	781		T5	148
valid_sources[0x0a]	265255	1			T2	7519		T3	918		T5	168
valid_sources[0x0b]	263459	1			T2	7338		T3	851		T5	195
valid_sources[0x0c]	267902	1			T2	7762		T3	938		T5	200
valid_sources[0x0d]	294736	1			T2	7681		T3	837		T5	154
valid_sources[0x0e]	270998	1			T2	7801		T3	866		T5	208
valid_sources[0x0f]	268362	1			T2	7609		T3	825		T5	226
valid_sources[0x10]	267360	1			T2	7510		T3	870		T5	166
valid_sources[0x11]	264189	1			T2	7549		T3	892		T5	210
valid_sources[0x12]	272379	1			T2	7608		T3	891		T5	167
valid_sources[0x13]	270038	1			T2	7682		T3	840		T5	203
valid_sources[0x14]	319042	1			T2	7475		T3	777		T5	209
valid_sources[0x15]	270536	1			T2	7806		T3	858		T5	134
valid_sources[0x16]	343548	1			T2	7621		T3	954		T5	133
valid_sources[0x17]	270538	1			T2	7667		T3	878		T5	217
valid_sources[0x18]	264451	1			T2	7466		T3	778		T5	118
valid_sources[0x19]	323834	1			T2	7556		T3	818		T5	200
valid_sources[0x1a]	279827	1			T2	7655		T3	785		T5	180
valid_sources[0x1b]	378287	1			T2	7514		T3	929		T5	122
valid_sources[0x1c]	612530	1			T2	7460		T3	775		T5	112
valid_sources[0x1d]	268440	1			T2	7423		T3	851		T5	193
valid_sources[0x1e]	342513	1			T2	7481		T3	911		T5	186
valid_sources[0x1f]	264842	1			T2	7500		T3	846		T5	158
valid_sources[0x20]	304147	1			T2	7590		T3	802		T5	188
valid_sources[0x21]	264148	1			T2	7720		T3	846		T5	175
valid_sources[0x22]	289860	1			T2	7747		T3	763		T5	173
valid_sources[0x23]	268429	1			T2	7892		T3	756		T5	175
valid_sources[0x24]	266029	1			T2	7606		T3	860		T5	160
valid_sources[0x25]	372319	1			T2	7343		T3	872		T5	137
valid_sources[0x26]	266388	1			T2	7651		T3	931		T5	208
valid_sources[0x27]	266251	1			T2	7657		T3	722		T5	203
valid_sources[0x28]	280481	1			T2	7272		T3	889		T5	168
valid_sources[0x29]	268983	1			T2	7533		T3	853		T5	200
valid_sources[0x2a]	297868	1			T2	7651		T3	902		T5	205
valid_sources[0x2b]	267985	1			T2	7682		T3	873		T5	190
valid_sources[0x2c]	382276	1			T2	7630		T3	951		T5	191
valid_sources[0x2d]	265241	1			T2	7643		T3	844		T5	210
valid_sources[0x2e]	284973	1			T2	7663		T3	878		T5	178
valid_sources[0x2f]	266084	1			T2	7807		T3	809		T5	180
valid_sources[0x30]	351634	1			T2	7803		T3	944		T5	140
valid_sources[0x31]	457565	1			T2	7619		T3	948		T5	170
valid_sources[0x32]	267725	1			T2	7496		T3	886		T5	118
valid_sources[0x33]	271980	1			T2	7698		T3	897		T5	221
valid_sources[0x34]	269465	1			T2	7656		T3	950		T5	218
valid_sources[0x35]	266446	1			T2	7658		T3	883		T5	140
valid_sources[0x36]	274819	1			T2	7513		T3	874		T5	132
valid_sources[0x37]	266332	1			T2	7757		T3	819		T5	187
valid_sources[0x38]	266874	1			T2	7462		T3	856		T5	190
valid_sources[0x39]	266725	1			T2	7606		T3	895		T5	250
valid_sources[0x3a]	268872	1			T2	7482		T3	766		T5	209
valid_sources[0x3b]	269163	1			T2	7687		T3	836		T5	216
valid_sources[0x3c]	274145	1			T2	7491		T3	859		T5	207
valid_sources[0x3d]	326704	1			T2	7657		T3	925		T5	206
valid_sources[0x3e]	310884	1			T2	7528		T3	798		T5	163
valid_sources[0x3f]	265215	1			T2	7335		T3	891		T5	204
valid_sources[0x40]	265948	1			T2	7866		T3	947		T5	236
valid_sources[0x41]	271053	1			T2	7412		T3	843		T5	219
valid_sources[0x42]	280118	1			T2	7606		T3	761		T5	181
valid_sources[0x43]	365881	1			T2	7671		T3	813		T5	201
valid_sources[0x44]	268054	1			T2	7567		T3	834		T5	266
valid_sources[0x45]	277284	1			T2	7507		T3	833		T5	200
valid_sources[0x46]	292240	1			T2	7567		T3	800		T5	179
valid_sources[0x47]	268530	1			T2	7510		T3	823		T5	198
valid_sources[0x48]	411414	1			T2	7676		T3	777		T5	185
valid_sources[0x49]	364787	1			T2	7623		T3	1083		T5	133
valid_sources[0x4a]	262216	1			T2	7266		T3	914		T5	155
valid_sources[0x4b]	267139	1			T2	7566		T3	954		T5	144
valid_sources[0x4c]	406869	1			T2	7662		T3	887		T5	227
valid_sources[0x4d]	279179	1			T2	7666		T3	861		T5	241
valid_sources[0x4e]	308350	1			T2	7427		T3	799		T5	288
valid_sources[0x4f]	274355	1			T2	7573		T3	916		T5	153
valid_sources[0x50]	371889	1			T2	7513		T3	833		T5	185
valid_sources[0x51]	307999	1			T2	7410		T3	895		T5	189
valid_sources[0x52]	558360	1			T2	7728		T3	849		T5	208
valid_sources[0x53]	262577	1			T2	7568		T3	847		T5	230
valid_sources[0x54]	2075800	1			T2	7471		T3	753		T5	164
valid_sources[0x55]	264768	1			T2	7468		T3	856		T5	224
valid_sources[0x56]	323977	1			T2	7561		T3	845		T5	150
valid_sources[0x57]	267551	1			T2	7433		T3	906		T5	216
valid_sources[0x58]	267253	1			T2	7562		T3	752		T5	177
valid_sources[0x59]	263788	1			T2	7602		T3	861		T5	225
valid_sources[0x5a]	265223	1			T2	7585		T3	1026		T5	241
valid_sources[0x5b]	266783	1			T2	7554		T3	913		T5	165
valid_sources[0x5c]	265284	1			T2	7565		T3	1011		T5	144
valid_sources[0x5d]	268463	1			T2	7502		T3	994		T5	164
valid_sources[0x5e]	2378902	1			T2	7515		T3	874		T5	199
valid_sources[0x5f]	267844	1			T2	7550		T3	841		T5	194
valid_sources[0x60]	268930	1			T2	7591		T3	753		T5	169
valid_sources[0x61]	314391	1			T2	7624		T3	927		T5	164
valid_sources[0x62]	398263	1			T2	7772		T3	988		T5	156
valid_sources[0x63]	264797	1			T2	7409		T3	978		T5	156
valid_sources[0x64]	295245	1			T2	7483		T3	921		T5	193
valid_sources[0x65]	268038	1			T2	7499		T3	985		T5	193
valid_sources[0x66]	276269	1			T2	7631		T3	838		T5	141
valid_sources[0x67]	266552	1			T2	7530		T3	854		T5	248
valid_sources[0x68]	276964	1			T2	7656		T3	838		T5	203
valid_sources[0x69]	264852	1			T2	7528		T3	836		T5	213
valid_sources[0x6a]	263593	1			T2	7219		T3	932		T5	195
valid_sources[0x6b]	265336	1			T2	7583		T3	839		T5	231
valid_sources[0x6c]	335342	1			T2	7734		T3	865		T5	178
valid_sources[0x6d]	263690	1			T2	7814		T3	833		T5	226
valid_sources[0x6e]	263851	1			T2	7604		T3	895		T5	137
valid_sources[0x6f]	407892	1			T2	7433		T3	762		T5	149
valid_sources[0x70]	268499	1			T2	7984		T3	767		T5	196
valid_sources[0x71]	509724	1			T2	7713		T3	886		T5	170
valid_sources[0x72]	269655	1			T2	7540		T3	854		T5	120
valid_sources[0x73]	266272	1			T1	1		T2	7528		T3	824
valid_sources[0x74]	266772	1			T2	7597		T3	836		T5	121
valid_sources[0x75]	267654	1			T2	7636		T3	877		T5	179
valid_sources[0x76]	270286	1			T2	7577		T3	791		T5	117
valid_sources[0x77]	267419	1			T2	7676		T3	824		T5	228
valid_sources[0x78]	262881	1			T2	7767		T3	895		T5	189
valid_sources[0x79]	264595	1			T2	7663		T3	815		T5	180
valid_sources[0x7a]	305768	1			T2	7690		T3	840		T5	217
valid_sources[0x7b]	345058	1			T2	7768		T3	835		T5	153
valid_sources[0x7c]	265002	1			T2	7448		T3	945		T5	163
valid_sources[0x7d]	381209	1			T2	7599		T3	881		T5	197
valid_sources[0x7e]	350374	1			T2	7606		T3	787		T5	196
valid_sources[0x7f]	272647	1			T2	7680		T3	932		T5	172
valid_sources[0x80]	270759	1			T2	7564		T3	777		T5	210

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19776896

1

T1

85781

T2

446793

T3

52756

values[0x0]

all_enables

biggest_size

11511000

1

T1

56459

T2

273255

T3

27687

values[0x1]

all_enables

biggest_size

9871181

1

T1

50024

T2

229195

T3

23255