Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

46369111

1

T1

183625

T2

994193

T3

116849

full_word

41364479

1

T1

192264

T2

949243

T3

103698

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	87733200	1			T1	375889		T2	194343		T3	220547
auto[TlIntgErrCmd]	132	1			T79	3		T80	13		T81	4
auto[TlIntgErrData]	119	1			T79	2		T80	6		T81	12
auto[TlIntgErrBoth]	139	1			T79	5		T80	11		T81	14

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41076924

1

T1

174483

T2

895803

T3

107364

auto[1]

46656666

1

T1

201406

T2

104763

T3

113183

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21218699	1			T1	88702		T2	449010		T3	54608
auto[TlIntgErrNone]	partial	auto[1]	25150052	1			T1	94923		T2	545183		T3	62241
auto[TlIntgErrNone]	full_word	auto[0]	19858044	1			T1	85781		T2	446793		T3	52756
auto[TlIntgErrNone]	full_word	auto[1]	21506405	1			T1	106483		T2	502450		T3	50942
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T79	1		T80	3		T142	3
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T79	1		T80	10		T81	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T79	1		T143	1		T144	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T145	1		T146	1		T147	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T79	2		T80	3		T81	4
auto[TlIntgErrData]	partial	auto[1]	58	1			T80	3		T81	7		T142	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T148	1		T149	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T81	1		T150	1		T151	1
auto[TlIntgErrBoth]	partial	auto[0]	62	1			T79	3		T80	7		T81	4
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T79	2		T80	4		T81	9
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T81	1		T140	1		T150	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T152	1		T145	2		T151	1