Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.44	100.00	93.85	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	498849863	1816888	0	0
intr_enable_rd_A	498849863	2965	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498849863	1816888	0	0
T6	867932	190503	0	0
T7	0	15003	0	0
T8	0	35372	0	0
T12	0	119416	0	0
T13	0	108052	0	0
T23	0	92654	0	0
T24	0	319721	0	0
T57	70957	0	0	0
T76	319453	0	0	0
T77	115558	0	0	0
T78	127515	0	0	0
T82	0	104453	0	0
T83	0	324215	0	0
T84	0	178629	0	0
T85	31442	0	0	0
T86	105142	0	0	0
T87	3105	0	0	0
T88	105646	0	0	0
T89	24596	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498849863	2965	0	0
T7	0	16	0	0
T12	0	166	0	0
T20	28085	0	0	0
T27	933369	13	0	0
T31	0	15	0	0
T66	1283	0	0	0
T90	0	27	0	0
T91	0	7	0	0
T92	0	38	0	0
T93	0	61	0	0
T94	0	13	0	0
T95	0	26	0	0
T96	292835	0	0	0
T97	178399	0	0	0
T98	104555	0	0	0
T99	315950	0	0	0
T100	101359	0	0	0
T101	509726	0	0	0
T102	181241	0	0	0