Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42601937

1

T1

106428

T2

45463

T3

3437

full_word

38286817

1

T1

83825

T2

37010

T3

3840

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	80888214	1			T1	190253		T2	82473		T3	7277
auto[TlIntgErrCmd]	188	1			T57	8		T58	10		T59	12
auto[TlIntgErrData]	183	1			T57	12		T58	12		T59	10
auto[TlIntgErrBoth]	169	1			T57	10		T58	8		T59	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38015734

1

T1

95311

T2

41461

T3

3658

auto[1]

42873020

1

T1

94942

T2

41012

T3

3619

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19536609	1			T1	47788		T2	20791		T3	1871
auto[TlIntgErrNone]	partial	auto[1]	23064825	1			T1	58640		T2	24672		T3	1566
auto[TlIntgErrNone]	full_word	auto[0]	18478893	1			T1	47523		T2	20670		T3	1787
auto[TlIntgErrNone]	full_word	auto[1]	19807887	1			T1	36302		T2	16340		T3	2053
auto[TlIntgErrCmd]	partial	auto[0]	65	1			T57	2		T58	3		T59	3
auto[TlIntgErrCmd]	partial	auto[1]	110	1			T57	4		T58	7		T59	9
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T57	1		T119	2		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T57	1		T121	2		T122	1
auto[TlIntgErrData]	partial	auto[0]	90	1			T57	8		T58	6		T59	5
auto[TlIntgErrData]	partial	auto[1]	82	1			T57	4		T58	6		T59	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T117	2		T120	1		T123	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T59	1		T117	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T57	5		T58	2		T59	5
auto[TlIntgErrBoth]	partial	auto[1]	95	1			T57	2		T58	6		T59	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T120	1		T124	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T57	3		T125	1		T119	1