Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.44	100.00	93.85	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	442602133	1309600	0	0
intr_enable_rd_A	442602133	3222	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442602133	1309600	0	0
T6	272353	92114	0	0
T7	0	101578	0	0
T8	0	298457	0	0
T11	0	3886	0	0
T12	0	12146	0	0
T13	0	191132	0	0
T22	0	50754	0	0
T23	0	67833	0	0
T60	0	136345	0	0
T61	0	87903	0	0
T62	227170	0	0	0
T63	403195	0	0	0
T64	462124	0	0	0
T65	208072	0	0	0
T66	34818	0	0	0
T67	72955	0	0	0
T68	20093	0	0	0
T69	3800	0	0	0
T70	155634	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442602133	3222	0	0
T8	0	287	0	0
T10	78215	0	0	0
T12	0	30	0	0
T13	0	120	0	0
T71	858466	74	0	0
T72	0	17	0	0
T73	0	44	0	0
T74	0	7	0	0
T75	0	64	0	0
T76	0	36	0	0
T77	0	64	0	0
T78	1454	0	0	0
T79	36770	0	0	0
T80	19139	0	0	0
T81	189061	0	0	0
T82	168414	0	0	0
T83	42170	0	0	0
T84	15379	0	0	0
T85	1049	0	0	0