Module Definition
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Module Instance : tb.dut.u_tlul_adapter.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.64 92.86 80.00 85.71 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.74 87.18 66.67 61.11 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.96 98.57 96.67 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.15 84.00 60.00 45.45



Module Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.93 92.31 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.08 86.84 62.96 62.50 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.96 98.57 96.67 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.15 84.00 60.00 45.45



Module Instance : tb.dut.u_msg_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.44 100.00 93.85 100.00 100.00 96.77 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_adapter.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.96 98.57 96.67 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_msg_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
90.93 92.31
tb.dut.u_tlul_adapter.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL151280.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
89.64 92.86
tb.dut.u_tlul_adapter.u_rspfifo

Line No.TotalCoveredPercent
TOTAL151386.67
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
90.93 71.43
tb.dut.u_tlul_adapter.u_sramreqfifo

TotalCoveredPercent
Conditions16531.25
Logical16531.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_msg_fifo

TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT18,T21,T24
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T10,T11
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
89.64 80.00
tb.dut.u_tlul_adapter.u_rspfifo

TotalCoveredPercent
Conditions24833.33
Logical24833.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_msg_fifo

SCOREBRANCH
89.64 85.71
tb.dut.u_tlul_adapter.u_rspfifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

SCOREBRANCH
90.93 100.00
tb.dut.u_tlul_adapter.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 535922216 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1726698040 57301579 0 0
gen_passthru_fifo.paramCheckPass 3960 3960 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 535922216 0 0
T1 3110632 874880 0 0
T2 1464712 377254 0 0
T3 442648 31998 0 0
T4 1097864 331323 0 0
T5 1213976 944875 0 0
T14 1854168 308309 0 0
T15 243184 51908 0 0
T16 9024 108 0 0
T17 8288 76 0 0
T18 648848 207654 0 0
T20 0 998530 0 0
T25 0 1511665 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3888290 3887760 0 0
T2 1830890 1830320 0 0
T3 553310 552620 0 0
T4 1372330 1371580 0 0
T5 1517470 1517040 0 0
T14 2317710 2317070 0 0
T15 303980 303250 0 0
T16 11280 10280 0 0
T17 10360 9630 0 0
T18 811060 810450 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3888290 3887760 0 0
T2 1830890 1830320 0 0
T3 553310 552620 0 0
T4 1372330 1371580 0 0
T5 1517470 1517040 0 0
T14 2317710 2317070 0 0
T15 303980 303250 0 0
T16 11280 10280 0 0
T17 10360 9630 0 0
T18 811060 810450 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3888290 3887760 0 0
T2 1830890 1830320 0 0
T3 553310 552620 0 0
T4 1372330 1371580 0 0
T5 1517470 1517040 0 0
T14 2317710 2317070 0 0
T15 303980 303250 0 0
T16 11280 10280 0 0
T17 10360 9630 0 0
T18 811060 810450 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1726698040 57301579 0 0
T1 777658 113868 0 0
T2 366178 47352 0 0
T3 110662 2890 0 0
T4 274466 68863 0 0
T5 303494 86511 0 0
T14 463542 68043 0 0
T15 60796 5276 0 0
T16 2256 0 0 0
T17 2072 0 0 0
T18 162212 56210 0 0
T20 0 467654 0 0
T25 0 921907 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 3960 3960 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T14 6 6 0 0
T15 6 6 0 0
T16 6 6 0 0
T17 6 6 0 0
T18 6 6 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Line No.TotalCoveredPercent
TOTAL141392.86
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
TotalCoveredPercent
Conditions10880.00
Logical10880.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11Excluded VC_COV_UNR

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 130 1 1 100.00
TERNARY 138 1 1 100.00
IF 69 3 3 100.00
IF 123 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded VC_COV_UNR


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncompleteExclusionExclude Annotation
DataKnown_A Excluded [UNSUPPORTED] excluded by fpv
DepthKnown_A 431674510 431609584 0 0
RvalidKnown_A 431674510 431609584 0 0
WreadyKnown_A 431674510 431609584 0 0
gen_normal_fifo.depthShallNotExceedParamDepth Excluded [UNSUPPORTED] excluded by fpv


DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL131292.31
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10800
ALWAYS11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 excluded
Exclude Annotation: [UNR] Pass is always '1'
111 1 1
112 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
TotalCoveredPercent
Conditions7571.43
Logical7571.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 138 1 1 100.00
IF 69 3 3 100.00
IF 111 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded VC_COV_UNR


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncompleteExclusionExclude Annotation
DataKnown_A Excluded [UNSUPPORTED] excluded by fpv
DepthKnown_A 431674510 431609584 0 0
RvalidKnown_A 431674510 431609584 0 0
WreadyKnown_A 431674510 431609584 0 0
gen_normal_fifo.depthShallNotExceedParamDepth Excluded [UNSUPPORTED] excluded by fpv


DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

Line Coverage for Instance : tb.dut.u_msg_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_msg_fifo
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT18,T21,T24
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101CoveredT9,T10,T11
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_msg_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_msg_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 431674510 21170421 0 0
DepthKnown_A 431674510 431609584 0 0
RvalidKnown_A 431674510 431609584 0 0
WreadyKnown_A 431674510 431609584 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 431674510 21170421 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 21170421 0 0
T1 388829 67086 0 0
T2 183089 27714 0 0
T3 55331 1674 0 0
T4 137233 44384 0 0
T5 151747 34937 0 0
T14 231771 9356 0 0
T15 30398 3268 0 0
T16 1128 0 0 0
T17 1036 0 0 0
T18 81106 38743 0 0
T20 0 202216 0 0
T25 0 627028 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 21170421 0 0
T1 388829 67086 0 0
T2 183089 27714 0 0
T3 55331 1674 0 0
T4 137233 44384 0 0
T5 151747 34937 0 0
T14 231771 9356 0 0
T15 30398 3268 0 0
T16 1128 0 0 0
T17 1036 0 0 0
T18 81106 38743 0 0
T20 0 202216 0 0
T25 0 627028 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T3,T4
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 431674510 36131158 0 0
DepthKnown_A 431674510 431609584 0 0
RvalidKnown_A 431674510 431609584 0 0
WreadyKnown_A 431674510 431609584 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 431674510 36131158 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 36131158 0 0
T1 388829 46782 0 0
T2 183089 19638 0 0
T3 55331 1216 0 0
T4 137233 24479 0 0
T5 151747 51574 0 0
T14 231771 58687 0 0
T15 30398 2008 0 0
T16 1128 0 0 0
T17 1036 0 0 0
T18 81106 17467 0 0
T20 0 265438 0 0
T25 0 294879 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 431609584 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 431674510 36131158 0 0
T1 388829 46782 0 0
T2 183089 19638 0 0
T3 55331 1216 0 0
T4 137233 24479 0 0
T5 151747 51574 0 0
T14 231771 58687 0 0
T15 30398 2008 0 0
T16 1128 0 0 0
T17 1036 0 0 0
T18 81106 17467 0 0
T20 0 265438 0 0
T25 0 294879 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 442602133 87753315 0 0
DepthKnown_A 442602133 442481850 0 0
RvalidKnown_A 442602133 442481850 0 0
WreadyKnown_A 442602133 442481850 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 87753315 0 0
T1 388829 190253 0 0
T2 183089 82479 0 0
T3 55331 7277 0 0
T4 137233 65615 0 0
T5 151747 214592 0 0
T14 231771 21849 0 0
T15 30398 11658 0 0
T16 1128 27 0 0
T17 1036 19 0 0
T18 81106 37861 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 442602133 152810776 0 0
DepthKnown_A 442602133 442481850 0 0
RvalidKnown_A 442602133 442481850 0 0
WreadyKnown_A 442602133 442481850 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 152810776 0 0
T1 388829 190253 0 0
T2 183089 82473 0 0
T3 55331 7277 0 0
T4 137233 65615 0 0
T5 151747 214590 0 0
T14 231771 98284 0 0
T15 30398 11658 0 0
T16 1128 27 0 0
T17 1036 19 0 0
T18 81106 37861 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 442602133 20960655 0 0
DepthKnown_A 442602133 442481850 0 0
RvalidKnown_A 442602133 442481850 0 0
WreadyKnown_A 442602133 442481850 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 20960655 0 0
T1 388829 46782 0 0
T2 183089 19638 0 0
T3 55331 1216 0 0
T4 137233 24479 0 0
T5 151747 51574 0 0
T14 231771 12978 0 0
T15 30398 2008 0 0
T16 1128 0 0 0
T17 1036 0 0 0
T18 81106 17467 0 0
T20 0 265438 0 0
T25 0 294879 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 442602133 37271341 0 0
DepthKnown_A 442602133 442481850 0 0
RvalidKnown_A 442602133 442481850 0 0
WreadyKnown_A 442602133 442481850 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 37271341 0 0
T1 388829 46782 0 0
T2 183089 19638 0 0
T3 55331 1216 0 0
T4 137233 24479 0 0
T5 151747 51574 0 0
T14 231771 58687 0 0
T15 30398 2008 0 0
T16 1128 0 0 0
T17 1036 0 0 0
T18 81106 17467 0 0
T20 0 265438 0 0
T25 0 294879 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 442602133 64285115 0 0
DepthKnown_A 442602133 442481850 0 0
RvalidKnown_A 442602133 442481850 0 0
WreadyKnown_A 442602133 442481850 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 64285115 0 0
T1 388829 143471 0 0
T2 183089 62839 0 0
T3 55331 6061 0 0
T4 137233 41136 0 0
T5 151747 163018 0 0
T14 231771 8871 0 0
T15 30398 9650 0 0
T16 1128 27 0 0
T17 1036 19 0 0
T18 81106 20394 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 442602133 115539435 0 0
DepthKnown_A 442602133 442481850 0 0
RvalidKnown_A 442602133 442481850 0 0
WreadyKnown_A 442602133 442481850 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 115539435 0 0
T1 388829 143471 0 0
T2 183089 62835 0 0
T3 55331 6061 0 0
T4 137233 41136 0 0
T5 151747 163016 0 0
T14 231771 39597 0 0
T15 30398 9650 0 0
T16 1128 27 0 0
T17 1036 19 0 0
T18 81106 20394 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 442602133 442481850 0 0
T1 388829 388776 0 0
T2 183089 183032 0 0
T3 55331 55262 0 0
T4 137233 137158 0 0
T5 151747 151704 0 0
T14 231771 231707 0 0
T15 30398 30325 0 0
T16 1128 1028 0 0
T17 1036 963 0 0
T18 81106 81045 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%