Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

46371746

1

T1

5

T2

38803

T7

22780

full_word

41597602

1

T1

3

T2

31226

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	87968958	1			T1	8		T2	70029		T3	1
auto[TlIntgErrCmd]	133	1			T65	14		T66	4		T67	4
auto[TlIntgErrData]	128	1			T65	6		T66	3		T67	3
auto[TlIntgErrBoth]	129	1			T65	10		T66	3		T67	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41155582

1

T1

1

T2

35215

T3

1

auto[1]

46813766

1

T1

7

T2

34814

T7

23001

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21248092	1			T1	1		T2	17586		T7	11432
auto[TlIntgErrNone]	partial	auto[1]	25123298	1			T1	4		T2	21217		T7	11348
auto[TlIntgErrNone]	full_word	auto[0]	19907306	1			T2	17629		T3	1		T7	11627
auto[TlIntgErrNone]	full_word	auto[1]	21690262	1			T1	3		T2	13597		T7	11653
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T65	7		T66	1		T142	3
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T65	5		T66	3		T67	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T65	1		T67	1		T140	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T65	1		T143	1		T144	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T65	5		T66	1		T67	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T65	1		T66	2		T67	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T142	1		T145	1		T146	2
auto[TlIntgErrData]	full_word	auto[1]	7	1			T147	1		T141	1		T143	2
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T65	1		T67	1		T142	9
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T65	8		T66	2		T67	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T66	1		T142	1		T143	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T65	1		T141	1		T148	1