Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	463427069	1910321	0	0
intr_enable_rd_A	463427069	2689	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463427069	1910321	0	0
T11	385734	133013	0	0
T12	0	25810	0	0
T13	0	55030	0	0
T17	0	233002	0	0
T18	0	14943	0	0
T19	0	226474	0	0
T24	0	237931	0	0
T69	0	136795	0	0
T70	0	385641	0	0
T71	0	11	0	0
T72	383504	0	0	0
T73	48977	0	0	0
T74	154918	0	0	0
T75	35868	0	0	0
T76	926270	0	0	0
T77	53441	0	0	0
T78	146854	0	0	0
T79	62359	0	0	0
T80	26997	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463427069	2689	0	0
T17	0	453	0	0
T18	0	4	0	0
T19	0	84	0	0
T81	885385	28	0	0
T82	0	18	0	0
T83	0	22	0	0
T84	0	37	0	0
T85	0	67	0	0
T86	0	40	0	0
T87	0	44	0	0
T88	614989	0	0	0
T89	58099	0	0	0
T90	150756	0	0	0
T91	630016	0	0	0
T92	189677	0	0	0
T93	171582	0	0	0
T94	105782	0	0	0
T95	9425	0	0	0
T96	80663	0	0	0