Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 42353897 1 T1 41040 T2 12038 T3 11187
full_word 38344306 1 T1 32606 T2 37751 T3 24891



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 80697853 1 T1 73646 T2 49789 T3 36078
auto[TlIntgErrCmd] 116 1 T54 4 T55 5 T56 13
auto[TlIntgErrData] 123 1 T54 6 T55 4 T56 7
auto[TlIntgErrBoth] 111 1 T55 11 T56 10 T106 4



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 38194584 1 T1 37002 T2 15084 T3 14058
auto[1] 42503619 1 T1 36644 T2 34705 T3 22020



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 19684486 1 T1 18664 T2 9077 T3 8517
auto[TlIntgErrNone] partial auto[1] 22669085 1 T1 22376 T2 2961 T3 2670
auto[TlIntgErrNone] full_word auto[0] 18509939 1 T1 18338 T2 6007 T3 5541
auto[TlIntgErrNone] full_word auto[1] 19834343 1 T1 14268 T2 31744 T3 19350
auto[TlIntgErrCmd] partial auto[0] 47 1 T54 2 T55 1 T56 5
auto[TlIntgErrCmd] partial auto[1] 60 1 T54 1 T55 4 T56 7
auto[TlIntgErrCmd] full_word auto[0] 2 1 T111 1 T112 1 - -
auto[TlIntgErrCmd] full_word auto[1] 7 1 T54 1 T56 1 T107 2
auto[TlIntgErrData] partial auto[0] 59 1 T54 4 T55 2 T56 5
auto[TlIntgErrData] partial auto[1] 55 1 T54 2 T55 2 T56 2
auto[TlIntgErrData] full_word auto[0] 6 1 T107 2 T113 1 T114 1
auto[TlIntgErrData] full_word auto[1] 3 1 T115 1 T116 1 T112 1
auto[TlIntgErrBoth] partial auto[0] 43 1 T55 2 T56 4 T106 3
auto[TlIntgErrBoth] partial auto[1] 62 1 T55 9 T56 6 T106 1
auto[TlIntgErrBoth] full_word auto[0] 2 1 T111 2 - - - -
auto[TlIntgErrBoth] full_word auto[1] 4 1 T109 1 T111 1 T108 1

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