Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	386217992	1146464	0	0
intr_enable_rd_A	386217992	4256	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386217992	1146464	0	0
T5	182275	31140	0	0
T6	244947	0	0	0
T7	0	71844	0	0
T10	377032	0	0	0
T11	0	88042	0	0
T14	0	113446	0	0
T15	0	106256	0	0
T23	470928	0	0	0
T24	7701	0	0	0
T35	0	106423	0	0
T36	0	89148	0	0
T37	146770	0	0	0
T39	566114	0	0	0
T40	825	0	0	0
T58	0	37679	0	0
T59	0	76762	0	0
T60	0	28916	0	0
T61	218205	0	0	0
T62	969	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386217992	4256	0	0
T11	0	219	0	0
T14	0	78	0	0
T15	0	171	0	0
T21	822430	0	0	0
T27	0	23	0	0
T38	405066	61	0	0
T58	0	72	0	0
T63	0	33	0	0
T64	0	67	0	0
T65	0	17	0	0
T66	0	37	0	0
T67	1118	0	0	0
T68	445206	0	0	0
T69	532776	0	0	0
T70	850	0	0	0
T71	114390	0	0	0
T72	690153	0	0	0
T73	1316	0	0	0
T74	59356	0	0	0