Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17597410	1			T1	4918		T2	26937		T3	478911
all_values[1]	17597410	1			T1	4918		T2	26937		T3	478911
all_values[2]	17597410	1			T1	4918		T2	26937		T3	478911

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

258848

1

T1

929

T8

411

T58

5264

auto[1]

52533382

1

T1

13825

T2

80811

T3

143673

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44719757

1

T1

12950

T2

62372

T3

125193

auto[1]

8072473

1

T1

1804

T2

18439

T3

184795

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	96122	1			T1	5		T58	2180		T16	2337
all_values[0]	auto[0]	auto[1]	370	1			T1	2		T58	2		T16	2
all_values[0]	auto[1]	auto[0]	17481774	1			T1	4904		T2	26930		T3	478525
all_values[0]	auto[1]	auto[1]	19144	1			T1	7		T2	7		T3	386
all_values[1]	auto[0]	auto[0]	88029	1			T1	922		T58	3082		T17	5
all_values[1]	auto[0]	auto[1]	225	1			T31	1		T34	2		T61	1
all_values[1]	auto[1]	auto[0]	17508857	1			T1	3996		T2	26937		T3	478911
all_values[1]	auto[1]	auto[1]	299	1			T31	5		T34	1		T61	6
all_values[2]	auto[0]	auto[0]	33394	1			T8	411		T31	2		T34	3
all_values[2]	auto[0]	auto[1]	40708	1			T9	176		T31	2		T57	1
all_values[2]	auto[1]	auto[0]	9511581	1			T1	3123		T2	8505		T3	294502
all_values[2]	auto[1]	auto[1]	8011727	1			T1	1795		T2	18432		T3	184409