Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127606

1

T1

14

T2

18

T3

390

auto[1]

136650

1

T1

12

T2

38

T7

18

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	97717	1			T1	12		T2	26		T3	61
len_1026_2046	7404	1			T21	8		T10	5		T6	37
len_514_1022	3136	1			T3	63		T29	1		T8	2
len_2_510	5988	1			T3	67		T4	2		T11	2
len_2056	170	1			T133	1		T68	3		T23	8
len_2048	289	1			T4	2		T6	1		T30	5
len_2040	171	1			T21	2		T30	2		T86	3
len_1032	185	1			T21	6		T30	3		T133	1
len_1024	1823	1			T3	1		T6	1		T30	5
len_1016	167	1			T3	1		T11	3		T21	2
len_520	150	1			T21	3		T134	2		T61	1
len_512	356	1			T21	6		T6	1		T30	3
len_504	194	1			T3	1		T21	2		T135	2
len_8	930	1			T15	6		T16	2		T17	2
len_0	13450	1			T1	1		T2	2		T3	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

112

1

T4

1

T6

1

T30

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	48947	1			T1	7		T2	8		T3	61
auto[0]	len_1026_2046	2857	1			T21	5		T10	4		T6	27
auto[0]	len_514_1022	1946	1			T3	63		T29	1		T10	2
auto[0]	len_2_510	3505	1			T3	67		T4	2		T21	1
auto[0]	len_2056	89	1			T133	1		T68	1		T23	2
auto[0]	len_2048	177	1			T30	3		T136	1		T137	1
auto[0]	len_2040	94	1			T21	1		T30	2		T86	2
auto[0]	len_1032	102	1			T21	2		T30	2		T133	1
auto[0]	len_1024	255	1			T3	1		T30	2		T31	1
auto[0]	len_1016	91	1			T3	1		T11	1		T21	2
auto[0]	len_520	80	1			T21	3		T134	2		T61	1
auto[0]	len_512	224	1			T21	5		T6	1		T30	1
auto[0]	len_504	123	1			T3	1		T135	2		T133	1
auto[0]	len_8	20	1			T135	1		T138	1		T61	1
auto[0]	len_0	5295	1			T2	1		T3	1		T7	1
auto[1]	len_2050_plus	48770	1			T1	5		T2	18		T7	9
auto[1]	len_1026_2046	4547	1			T21	3		T10	1		T6	10
auto[1]	len_514_1022	1190	1			T8	2		T5	1		T21	1
auto[1]	len_2_510	2483	1			T11	2		T21	3		T10	105
auto[1]	len_2056	81	1			T68	2		T23	6		T139	2
auto[1]	len_2048	112	1			T4	2		T6	1		T30	2
auto[1]	len_2040	77	1			T21	1		T86	1		T140	2
auto[1]	len_1032	83	1			T21	4		T30	1		T61	3
auto[1]	len_1024	1568	1			T6	1		T30	3		T91	92
auto[1]	len_1016	76	1			T11	2		T140	1		T23	2
auto[1]	len_520	70	1			T141	2		T68	2		T23	9
auto[1]	len_512	132	1			T21	1		T30	2		T16	1
auto[1]	len_504	71	1			T21	2		T68	5		T23	3
auto[1]	len_8	910	1			T15	6		T16	2		T17	2
auto[1]	len_0	8155	1			T1	1		T2	1		T29	50

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

62

1

T6

1

T137

3

T142

2

auto[1]

len_upper

50

1

T4

1

T30

1

T87

2