Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4251476

1

T1

884

T2

3991

T3

147407

auto[1]

2739618

1

T1

1545

T2

2260

T7

1603

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2689783

1

T1

1294

T2

5856

T7

2402

auto[1]

4301311

1

T1

1135

T2

395

T3

147407

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3212812

1

T1

1110

T2

3728

T3

147407

auto[1]

3778282

1

T1

1319

T2

2523

T7

1810

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4201568

1

T1

1225

T2

3583

T3

147407

auto[1]

2789526

1

T1

1204

T2

2668

T7

2524

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6333283	1			T1	2401		T2	6210		T3	128157
fifo_depth[1]	112512	1			T1	20		T2	38		T3	4796
fifo_depth[2]	88510	1			T1	7		T2	3		T3	4511
fifo_depth[3]	70389	1			T1	1		T3	3519		T29	11
fifo_depth[4]	62974	1			T3	2375		T29	10		T8	49
fifo_depth[5]	49312	1			T3	1610		T29	11		T8	56
fifo_depth[6]	39345	1			T3	1095		T29	10		T8	31
fifo_depth[7]	26228	1			T3	738		T29	11		T8	29

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657811

1

T1

28

T2

41

T3

19250

auto[1]

6333283

1

T1

2401

T2

6210

T3

128157

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6981212

1

T1

2429

T2

6251

T3

147407

auto[1]

9882

1

T10

79

T30

376

T31

295

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

29066

1

T1

4

T2

11

T11

32

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

34444

1

T7

3

T8

95

T11

29

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

21969

1

T8

15

T5

6

T11

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

43675

1

T2

7

T7

3

T8

59

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

162017

1

T3

19250

T4

94

T11

12

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28055

1

T1

3

T11

18

T6

31

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

26520

1

T1

5

T29

576

T4

30

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28222

1

T8

78

T4

15

T5

16

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

33457

1

T4

23

T5

9

T58

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

36953

1

T2

13

T7

4

T5

13

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

34545

1

T2

2

T4

24

T11

16

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

36334

1

T1

5

T2

4

T4

72

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

38718

1

T8

11

T11

21

T15

1103

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

27554

1

T2

4

T4

19

T5

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

36919

1

T1

11

T7

12

T4

65

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

39363

1

T8

80

T4

18

T11

23

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

181855

1

T1

198

T2

2609

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

151801

1

T1

424

T2

2

T7

436

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

175815

1

T2

316

T7

225

T8

56

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

198594

1

T1

1

T2

780

T7

477

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1580808

1

T1

1

T2

1

T3

128157

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

181329

1

T1

254

T2

1

T4

205

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

187670

1

T1

220

T29

36

T4

860

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

180972

1

T2

1

T7

347

T8

258

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

382199

1

T2

389

T7

1

T29

91

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

440500

1

T2

575

T7

1252

T29

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

436571

1

T1

449

T2

251

T29

90

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

452005

1

T1

213

T2

897

T8

339

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

485718

1

T2

2

T7

1

T8

9

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

457002

1

T2

384

T7

1

T29

102

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

387721

1

T1

337

T2

2

T7

538

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

452723

1

T1

304

T7

1

T8

127

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

210287

1

T1

202

T2

2620

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

184184

1

T1

424

T2

2

T7

439

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

197661

1

T2

316

T7

225

T8

71

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

241505

1

T1

1

T2

787

T7

480

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1740474

1

T1

1

T2

1

T3

147407

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

208968

1

T1

257

T2

1

T4

205

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

214001

1

T1

225

T29

612

T4

890

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

208446

1

T2

1

T7

347

T8

336

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

414907

1

T2

389

T7

1

T29

91

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

476947

1

T2

588

T7

1256

T29

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

470998

1

T1

449

T2

253

T29

90

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

488202

1

T1

218

T2

901

T8

339

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

524163

1

T2

2

T7

1

T8

20

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

484397

1

T2

388

T7

1

T29

102

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

424437

1

T1

348

T2

2

T7

550

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

491635

1

T1

304

T7

1

T8

207

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

634

1

T31

94

T61

8

T144

104

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2061

1

T30

5

T31

6

T61

91

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

123

1

T10

31

T31

7

T61

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

764

1

T61

117

T145

2

T144

17

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

2351

1

T30

61

T31

162

T72

466

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

416

1

T30

1

T31

12

T61

23

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

189

1

T30

44

T123

5

T72

40

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

748

1

T30

124

T123

2

T32

350

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

749

1

T30

22

T61

4

T144

510

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

506

1

T30

119

T123

3

T146

46

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

118

1

T10

48

T31

6

T123

10

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

137

1

T61

5

T32

1

T96

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

273

1

T123

14

T72

87

T19

20

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

159

1

T145

4

T26

9

T147

66

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

203

1

T148

11

T96

14

T149

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

451

1

T31

8

T144

17

T96

4

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

181855

1

T1

198

T2

2609

T7

1

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

151801

1

T1

424

T2

2

T7

436

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

175815

1

T2

316

T7

225

T8

56

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

198594

1

T1

1

T2

780

T7

477

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1580808

1

T1

1

T2

1

T3

128157

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

181329

1

T1

254

T2

1

T4

205

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

187670

1

T1

220

T29

36

T4

860

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

180972

1

T2

1

T7

347

T8

258

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

382199

1

T2

389

T7

1

T29

91

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

440500

1

T2

575

T7

1252

T29

7

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

436571

1

T1

449

T2

251

T29

90

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

452005

1

T1

213

T2

897

T8

339

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

485718

1

T2

2

T7

1

T8

9

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

457002

1

T2

384

T7

1

T29

102

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

387721

1

T1

337

T2

2

T7

538

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

452723

1

T1

304

T7

1

T8

127

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3574

1

T1

4

T2

11

T11

17

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

2888

1

T7

3

T8

14

T11

22

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3298

1

T8

3

T5

6

T11

3

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

4280

1

T2

6

T7

3

T8

9

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

41022

1

T3

4796

T4

70

T11

9

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3312

1

T1

3

T11

9

T6

1

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3507

1

T1

4

T29

11

T4

16

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3583

1

T8

10

T4

7

T5

15

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5244

1

T4

11

T5

6

T58

5

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5889

1

T2

12

T7

3

T5

13

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5734

1

T2

2

T4

13

T11

10

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6002

1

T1

3

T2

4

T4

40

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7765

1

T8

2

T11

13

T15

190

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5193

1

T2

3

T4

9

T5

2

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

5342

1

T1

6

T7

10

T4

39

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5879

1

T8

15

T4

10

T11

13

fifo_depth[2]

auto[0]

auto[0]

auto[0]

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