Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17597410	1			T1	4918		T2	26937		T3	478911
all_pins[1]	17597410	1			T1	4918		T2	26937		T3	478911
all_pins[2]	17597410	1			T1	4918		T2	26937		T3	478911

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44760242	1			T1	12951		T2	62372		T3	125193
values[0x1]	8031988	1			T1	1803		T2	18439		T3	184795
transitions[0x0=>0x1]	8031840	1			T1	1803		T2	18439		T3	184795
transitions[0x1=>0x0]	8031849	1			T1	1803		T2	18439		T3	184795

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17577470	1			T1	4910		T2	26930		T3	478525
all_pins[0]	values[0x1]	19940	1			T1	8		T2	7		T3	386
all_pins[0]	transitions[0x0=>0x1]	19883	1			T1	8		T2	7		T3	386
all_pins[0]	transitions[0x1=>0x0]	8011679	1			T1	1795		T2	18432		T3	184409
all_pins[1]	values[0x0]	17597089	1			T1	4918		T2	26937		T3	478911
all_pins[1]	values[0x1]	321	1			T31	5		T34	1		T61	6
all_pins[1]	transitions[0x0=>0x1]	278	1			T31	5		T34	1		T61	4
all_pins[1]	transitions[0x1=>0x0]	19897	1			T1	8		T2	7		T3	386
all_pins[2]	values[0x0]	9585683	1			T1	3123		T2	8505		T3	294502
all_pins[2]	values[0x1]	8011727	1			T1	1795		T2	18432		T3	184409
all_pins[2]	transitions[0x0=>0x1]	8011679	1			T1	1795		T2	18432		T3	184409
all_pins[2]	transitions[0x1=>0x0]	273	1			T31	5		T61	6		T123	1