Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1031 1 T31 4 T34 7 T61 10
all_values[1] 1031 1 T31 4 T34 7 T61 10
all_values[2] 1031 1 T31 4 T34 7 T61 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1541 1 T31 5 T34 5 T61 12
auto[1] 1552 1 T31 7 T34 16 T61 18


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1141 1 T31 2 T34 9 T61 14
auto[1] 1952 1 T31 10 T34 12 T61 16


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1783 1 T31 5 T34 12 T61 19
auto[1] 1310 1 T31 7 T34 9 T61 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 202 1 T34 2 T61 1 T22 12
all_values[0] auto[0] auto[0] auto[1] 97 1 T31 1 T22 6 T23 2
all_values[0] auto[0] auto[1] auto[0] 202 1 T31 1 T34 2 T61 1
all_values[0] auto[0] auto[1] auto[1] 96 1 T61 1 T22 2 T23 3
all_values[0] auto[1] auto[0] auto[1] 235 1 T31 1 T61 1 T22 7
all_values[0] auto[1] auto[1] auto[1] 199 1 T31 1 T34 3 T61 6
all_values[1] auto[0] auto[0] auto[0] 185 1 T61 3 T22 9 T24 2
all_values[1] auto[0] auto[0] auto[1] 127 1 T31 1 T22 4 T23 1
all_values[1] auto[0] auto[1] auto[0] 156 1 T34 2 T61 2 T22 7
all_values[1] auto[0] auto[1] auto[1] 130 1 T34 2 T61 2 T22 8
all_values[1] auto[1] auto[0] auto[1] 208 1 T34 3 T61 1 T22 10
all_values[1] auto[1] auto[1] auto[1] 225 1 T31 3 T61 2 T22 10
all_values[2] auto[0] auto[0] auto[0] 191 1 T61 3 T22 8 T23 4
all_values[2] auto[0] auto[0] auto[1] 99 1 T31 1 T61 2 T22 7
all_values[2] auto[0] auto[1] auto[0] 205 1 T31 1 T34 3 T61 4
all_values[2] auto[0] auto[1] auto[1] 93 1 T34 1 T22 3 T24 5
all_values[2] auto[1] auto[0] auto[1] 197 1 T31 1 T61 1 T22 6
all_values[2] auto[1] auto[1] auto[1] 246 1 T31 1 T34 3 T22 16


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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