Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4356	1			T1	2		T2	8		T7	1
sha2_none	4136	1			T1	1		T2	3		T7	1
sha2_512	7627	1			T1	1		T2	9		T7	6
sha2_384	6967	1			T1	4		T2	3		T3	386
sha2_256	6273	1			T1	2		T2	4		T7	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18382

1

T1

5

T2

16

T3

386

auto[1]

11380

1

T1

6

T2

11

T7

6

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11232

1

T1

6

T2

21

T7

9

auto[1]

18530

1

T1

5

T2

6

T3

386

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15310

1

T1

4

T2

16

T7

5

disabled

14452

1

T1

7

T2

11

T3

386

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4798	1			T1	2		T2	3		T7	2
key_none	7422	1			T1	3		T2	6		T3	386
key_1024	4381	1			T1	1		T2	3		T29	3
key_512	3800	1			T1	3		T2	2		T7	3
key_384	3274	1			T2	4		T8	1		T4	5
key_256	3090	1			T1	2		T2	7		T7	4
key_128	2919	1			T2	2		T7	1		T29	1

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18442

1

T1

5

T2

13

T3

386

auto[1]

11320

1

T1

6

T2

14

T7

6

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29513

1

T1

11

T2

24

T3

386

disabled

249

1

T2

3

T7

2

T57

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1561

1

T2

2

T7

1

T29

1

enabled

auto[0]

auto[0]

auto[1]

1569

1

T2

3

T7

2

T29

2

enabled

auto[0]

auto[1]

auto[0]

1565

1

T1

1

T2

2

T29

2

enabled

auto[0]

auto[1]

auto[1]

1616

1

T1

1

T2

4

T8

1

enabled

auto[1]

auto[0]

auto[0]

4249

1

T2

2

T7

1

T8

1

enabled

auto[1]

auto[0]

auto[1]

1567

1

T2

1

T29

1

T8

1

enabled

auto[1]

auto[1]

auto[0]

1616

1

T1

1

T2

2

T7

1

enabled

auto[1]

auto[1]

auto[1]

1567

1

T1

1

T8

1

T4

5

disabled

auto[0]

auto[0]

auto[0]

1274

1

T1

1

T2

4

T7

1

disabled

auto[0]

auto[0]

auto[1]

1164

1

T1

2

T2

3

T7

1

disabled

auto[0]

auto[1]

auto[0]

1238

1

T2

1

T7

2

T8

1

disabled

auto[0]

auto[1]

auto[1]

1245

1

T1

1

T2

2

T7

2

disabled

auto[1]

auto[0]

auto[0]

5679

1

T1

1

T3

386

T29

1

disabled

auto[1]

auto[0]

auto[1]

1319

1

T1

1

T2

1

T4

1

disabled

auto[1]

auto[1]

auto[0]

1260

1

T1

1

T29

2

T4

3

disabled

auto[1]

auto[1]

auto[1]

1273

1

T7

1

T29

1

T8

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15221

1

T1

4

T2

15

T7

3

enabled

disabled

89

1

T2

1

T7

2

T57

1

disabled

disabled

160

1

T2

2

T57

3

T90

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14292

1

T1

7

T2

9

T3

386

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1236	1			T1	1		T2	2		T4	3
key_invalid	sha2_none	823	1			T29	1		T8	1		T4	2
key_invalid	sha2_512	911	1			T29	2		T11	1		T21	1
key_invalid	sha2_384	871	1			T2	1		T4	4		T21	1
key_invalid	sha2_256	847	1			T1	1		T7	2		T29	1
key_none	sha2_invalid	528	1			T1	1		T2	2		T7	1
key_none	sha2_none	571	1			T2	1		T8	1		T11	2
key_none	sha2_512	2532	1			T2	1		T7	1		T4	1
key_none	sha2_384	2151	1			T1	2		T2	1		T3	386
key_none	sha2_256	1590	1			T2	1		T5	2		T11	1
key_1024	sha2_invalid	533	1			T4	1		T21	3		T10	1
key_1024	sha2_none	571	1			T4	1		T21	2		T10	1
key_1024	sha2_512	1731	1			T2	2		T8	1		T4	3
key_1024	sha2_384	910	1			T1	1		T2	1		T8	1
key_512	sha2_invalid	481	1			T8	1		T4	1		T21	1
key_512	sha2_none	547	1			T1	1		T2	1		T7	1
key_512	sha2_512	622	1			T7	1		T8	1		T4	1
key_512	sha2_384	1245	1			T1	1		T7	1		T8	1
key_512	sha2_256	856	1			T1	1		T2	1		T8	1
key_384	sha2_invalid	513	1			T2	2		T4	2		T5	1
key_384	sha2_none	531	1			T4	2		T11	1		T21	1
key_384	sha2_512	607	1			T2	1		T5	2		T11	2
key_384	sha2_384	545	1			T8	1		T11	1		T21	3
key_384	sha2_256	1039	1			T2	1		T4	1		T11	1
key_256	sha2_invalid	519	1			T2	2		T4	2		T21	2
key_256	sha2_none	524	1			T2	1		T4	1		T21	1
key_256	sha2_512	639	1			T1	1		T2	3		T7	3
key_256	sha2_384	611	1			T7	1		T29	1		T4	3
key_256	sha2_256	750	1			T2	1		T11	1		T10	1
key_128	sha2_invalid	532	1			T11	1		T21	1		T17	2
key_128	sha2_none	554	1			T8	1		T11	1		T21	2
key_128	sha2_512	570	1			T2	2		T7	1		T29	1
key_128	sha2_384	616	1			T6	1		T30	2		T15	1
key_128	sha2_256	599	1			T8	1		T9	1		T10	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

577

1

T29

2

T4

1

T5

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1236	1			T1	1		T2	2		T4	3
key_invalid	sha2_none	823	1			T29	1		T8	1		T4	2
key_invalid	sha2_512	911	1			T29	2		T11	1		T21	1
key_invalid	sha2_384	871	1			T2	1		T4	4		T21	1
key_invalid	sha2_256	847	1			T1	1		T7	2		T29	1
key_none	sha2_invalid	528	1			T1	1		T2	2		T7	1
key_none	sha2_none	571	1			T2	1		T8	1		T11	2
key_none	sha2_512	2532	1			T2	1		T7	1		T4	1
key_none	sha2_384	2151	1			T1	2		T2	1		T3	386
key_none	sha2_256	1590	1			T2	1		T5	2		T11	1
key_1024	sha2_invalid	533	1			T4	1		T21	3		T10	1
key_1024	sha2_none	571	1			T4	1		T21	2		T10	1
key_1024	sha2_512	1731	1			T2	2		T8	1		T4	3
key_1024	sha2_384	910	1			T1	1		T2	1		T8	1
key_1024	sha2_256	577	1			T29	2		T4	1		T5	1
key_512	sha2_invalid	481	1			T8	1		T4	1		T21	1
key_512	sha2_none	547	1			T1	1		T2	1		T7	1
key_512	sha2_512	622	1			T7	1		T8	1		T4	1
key_512	sha2_384	1245	1			T1	1		T7	1		T8	1
key_512	sha2_256	856	1			T1	1		T2	1		T8	1
key_384	sha2_invalid	513	1			T2	2		T4	2		T5	1
key_384	sha2_none	531	1			T4	2		T11	1		T21	1
key_384	sha2_512	607	1			T2	1		T5	2		T11	2
key_384	sha2_384	545	1			T8	1		T11	1		T21	3
key_384	sha2_256	1039	1			T2	1		T4	1		T11	1
key_256	sha2_invalid	519	1			T2	2		T4	2		T21	2
key_256	sha2_none	524	1			T2	1		T4	1		T21	1
key_256	sha2_512	639	1			T1	1		T2	3		T7	3
key_256	sha2_384	611	1			T7	1		T29	1		T4	3
key_256	sha2_256	750	1			T2	1		T11	1		T10	1
key_128	sha2_invalid	532	1			T11	1		T21	1		T17	2
key_128	sha2_none	554	1			T8	1		T11	1		T21	2
key_128	sha2_512	570	1			T2	2		T7	1		T29	1
key_128	sha2_384	616	1			T6	1		T30	2		T15	1
key_128	sha2_256	599	1			T8	1		T9	1		T10	1