Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.61 95.40 97.17 100.00 94.12 98.27 98.48 99.85


Total test records in report: 658
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T532 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3556481547 Jul 07 05:28:16 PM PDT 24 Jul 07 05:28:17 PM PDT 24 41987685 ps
T533 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2315851194 Jul 07 05:28:50 PM PDT 24 Jul 07 05:28:53 PM PDT 24 275879101 ps
T534 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1248632978 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:38 PM PDT 24 15759194 ps
T535 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.4147305800 Jul 07 05:28:32 PM PDT 24 Jul 07 05:28:37 PM PDT 24 72211806 ps
T100 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1139645771 Jul 07 05:28:28 PM PDT 24 Jul 07 05:28:30 PM PDT 24 33460352 ps
T536 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1289030805 Jul 07 05:28:40 PM PDT 24 Jul 07 05:28:43 PM PDT 24 76693086 ps
T537 /workspace/coverage/cover_reg_top/10.hmac_intr_test.64424745 Jul 07 05:28:34 PM PDT 24 Jul 07 05:28:35 PM PDT 24 17079834 ps
T101 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1901112631 Jul 07 05:28:24 PM PDT 24 Jul 07 05:28:25 PM PDT 24 26552159 ps
T538 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2966288317 Jul 07 05:28:42 PM PDT 24 Jul 07 05:28:44 PM PDT 24 37036040 ps
T539 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3611930793 Jul 07 05:28:38 PM PDT 24 Jul 07 05:28:41 PM PDT 24 210998712 ps
T540 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.710752033 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:38 PM PDT 24 215835651 ps
T75 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2957441848 Jul 07 05:28:22 PM PDT 24 Jul 07 05:28:25 PM PDT 24 981420442 ps
T115 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3426059508 Jul 07 05:28:40 PM PDT 24 Jul 07 05:28:43 PM PDT 24 304261105 ps
T541 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.892538303 Jul 07 05:28:28 PM PDT 24 Jul 07 05:28:29 PM PDT 24 19797475 ps
T76 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1768869601 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:42 PM PDT 24 902314544 ps
T542 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1122150362 Jul 07 05:28:26 PM PDT 24 Jul 07 05:28:29 PM PDT 24 90763120 ps
T543 /workspace/coverage/cover_reg_top/8.hmac_intr_test.907596539 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:36 PM PDT 24 10713601 ps
T544 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1039078833 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:39 PM PDT 24 93137948 ps
T545 /workspace/coverage/cover_reg_top/39.hmac_intr_test.4000031030 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:38 PM PDT 24 35292784 ps
T546 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3339428950 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:44 PM PDT 24 94491452 ps
T116 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1017979193 Jul 07 05:28:32 PM PDT 24 Jul 07 05:28:34 PM PDT 24 121074253 ps
T547 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4008557923 Jul 07 05:28:13 PM PDT 24 Jul 07 05:28:16 PM PDT 24 300903620 ps
T548 /workspace/coverage/cover_reg_top/2.hmac_intr_test.43666349 Jul 07 05:28:13 PM PDT 24 Jul 07 05:28:14 PM PDT 24 30385085 ps
T549 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1956728854 Jul 07 05:28:18 PM PDT 24 Jul 07 05:28:19 PM PDT 24 26056597 ps
T117 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2138222663 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:38 PM PDT 24 64640965 ps
T102 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1218109733 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:43 PM PDT 24 28503365 ps
T126 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4034940972 Jul 07 05:28:27 PM PDT 24 Jul 07 05:28:30 PM PDT 24 174848635 ps
T103 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1360787846 Jul 07 05:28:29 PM PDT 24 Jul 07 05:28:31 PM PDT 24 17301862 ps
T550 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2780755170 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:40 PM PDT 24 44615783 ps
T551 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1662867340 Jul 07 05:28:24 PM PDT 24 Jul 07 05:28:26 PM PDT 24 102990563 ps
T118 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3024032756 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:39 PM PDT 24 209916856 ps
T125 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4128929337 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:40 PM PDT 24 467255369 ps
T552 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2692335031 Jul 07 05:28:55 PM PDT 24 Jul 07 05:28:56 PM PDT 24 51122054 ps
T553 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2164840854 Jul 07 05:28:25 PM PDT 24 Jul 07 05:28:40 PM PDT 24 618877968 ps
T124 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.72113919 Jul 07 05:28:34 PM PDT 24 Jul 07 05:28:39 PM PDT 24 3091641889 ps
T119 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1319682391 Jul 07 05:28:49 PM PDT 24 Jul 07 05:28:51 PM PDT 24 132562563 ps
T554 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4282329166 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:39 PM PDT 24 372044199 ps
T555 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1952588390 Jul 07 05:28:25 PM PDT 24 Jul 07 05:28:30 PM PDT 24 311015715 ps
T132 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1084110906 Jul 07 05:28:17 PM PDT 24 Jul 07 05:28:21 PM PDT 24 500223920 ps
T556 /workspace/coverage/cover_reg_top/7.hmac_intr_test.951791558 Jul 07 05:28:33 PM PDT 24 Jul 07 05:28:34 PM PDT 24 43861914 ps
T120 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2399008661 Jul 07 05:28:21 PM PDT 24 Jul 07 05:28:24 PM PDT 24 127095042 ps
T557 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2195616365 Jul 07 05:28:15 PM PDT 24 Jul 07 05:28:19 PM PDT 24 147825627 ps
T558 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2342232227 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:37 PM PDT 24 278721319 ps
T559 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3770147673 Jul 07 05:28:34 PM PDT 24 Jul 07 05:28:37 PM PDT 24 113688403 ps
T129 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.766504240 Jul 07 05:28:26 PM PDT 24 Jul 07 05:28:28 PM PDT 24 50586952 ps
T560 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3721224055 Jul 07 05:28:32 PM PDT 24 Jul 07 05:28:36 PM PDT 24 96528682 ps
T561 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2880373642 Jul 07 05:28:32 PM PDT 24 Jul 07 05:28:33 PM PDT 24 25651790 ps
T562 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4028574969 Jul 07 05:28:24 PM PDT 24 Jul 07 05:28:31 PM PDT 24 428151426 ps
T563 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.233808838 Jul 07 05:28:32 PM PDT 24 Jul 07 05:28:34 PM PDT 24 41602080 ps
T128 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3706185269 Jul 07 05:28:39 PM PDT 24 Jul 07 05:28:45 PM PDT 24 877666502 ps
T564 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2794347101 Jul 07 05:28:18 PM PDT 24 Jul 07 05:28:20 PM PDT 24 21766264 ps
T565 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3737808170 Jul 07 05:28:28 PM PDT 24 Jul 07 05:28:30 PM PDT 24 143303708 ps
T566 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2138661034 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:42 PM PDT 24 703073053 ps
T567 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2797952149 Jul 07 05:28:47 PM PDT 24 Jul 07 05:28:48 PM PDT 24 43172782 ps
T568 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.639627341 Jul 07 05:28:31 PM PDT 24 Jul 07 05:28:34 PM PDT 24 57255758 ps
T569 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3543534133 Jul 07 05:28:30 PM PDT 24 Jul 07 05:28:31 PM PDT 24 38290311 ps
T570 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2330965985 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:41 PM PDT 24 203255546 ps
T571 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1133681574 Jul 07 05:28:34 PM PDT 24 Jul 07 05:28:38 PM PDT 24 136158667 ps
T572 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2497729346 Jul 07 05:28:54 PM PDT 24 Jul 07 05:28:55 PM PDT 24 16140362 ps
T573 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3907523554 Jul 07 05:28:52 PM PDT 24 Jul 07 05:28:53 PM PDT 24 41715961 ps
T574 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2711976966 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:43 PM PDT 24 12414734 ps
T575 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3075370556 Jul 07 05:28:40 PM PDT 24 Jul 07 05:28:43 PM PDT 24 14898488 ps
T576 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2718486246 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:40 PM PDT 24 40265041 ps
T577 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1607823322 Jul 07 05:28:24 PM PDT 24 Jul 07 05:28:28 PM PDT 24 218144156 ps
T578 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.925038095 Jul 07 05:28:27 PM PDT 24 Jul 07 05:28:29 PM PDT 24 62082784 ps
T579 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3249302028 Jul 07 05:28:27 PM PDT 24 Jul 07 05:28:28 PM PDT 24 41831005 ps
T580 /workspace/coverage/cover_reg_top/30.hmac_intr_test.365830077 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:36 PM PDT 24 14760807 ps
T581 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.804816467 Jul 07 05:28:24 PM PDT 24 Jul 07 05:28:26 PM PDT 24 96405327 ps
T582 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2949463735 Jul 07 05:28:56 PM PDT 24 Jul 07 05:28:57 PM PDT 24 14355105 ps
T583 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.584586357 Jul 07 05:28:54 PM PDT 24 Jul 07 05:28:56 PM PDT 24 338662266 ps
T584 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1386631039 Jul 07 05:28:21 PM PDT 24 Jul 07 05:28:23 PM PDT 24 281503215 ps
T585 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.6149976 Jul 07 05:28:28 PM PDT 24 Jul 07 05:28:32 PM PDT 24 142098671 ps
T586 /workspace/coverage/cover_reg_top/49.hmac_intr_test.849085104 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:39 PM PDT 24 63135927 ps
T127 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3944807092 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:43 PM PDT 24 220888205 ps
T587 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3161175627 Jul 07 05:28:29 PM PDT 24 Jul 07 05:28:31 PM PDT 24 184283430 ps
T588 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2073049260 Jul 07 05:28:30 PM PDT 24 Jul 07 05:28:32 PM PDT 24 22098790 ps
T589 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1873407032 Jul 07 05:28:43 PM PDT 24 Jul 07 05:28:46 PM PDT 24 157059556 ps
T590 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3884815972 Jul 07 05:28:25 PM PDT 24 Jul 07 05:28:34 PM PDT 24 696354511 ps
T591 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3277460108 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:39 PM PDT 24 38139587 ps
T592 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1694737300 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:38 PM PDT 24 34414058 ps
T593 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4190570533 Jul 07 05:28:23 PM PDT 24 Jul 07 05:28:25 PM PDT 24 291440535 ps
T594 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.695571560 Jul 07 05:28:13 PM PDT 24 Jul 07 05:28:15 PM PDT 24 247960463 ps
T595 /workspace/coverage/cover_reg_top/33.hmac_intr_test.769486203 Jul 07 05:28:28 PM PDT 24 Jul 07 05:28:29 PM PDT 24 15908961 ps
T104 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1326625367 Jul 07 05:28:24 PM PDT 24 Jul 07 05:28:30 PM PDT 24 1237903187 ps
T596 /workspace/coverage/cover_reg_top/1.hmac_intr_test.998413548 Jul 07 05:28:21 PM PDT 24 Jul 07 05:28:22 PM PDT 24 26115192 ps
T597 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.793477930 Jul 07 05:28:19 PM PDT 24 Jul 07 05:28:22 PM PDT 24 1923765564 ps
T105 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2060451962 Jul 07 05:28:29 PM PDT 24 Jul 07 05:28:30 PM PDT 24 36902575 ps
T598 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2597269880 Jul 07 05:28:57 PM PDT 24 Jul 07 05:28:58 PM PDT 24 67352790 ps
T599 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2628345543 Jul 07 05:28:33 PM PDT 24 Jul 07 05:28:35 PM PDT 24 20037919 ps
T600 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2704480338 Jul 07 05:28:22 PM PDT 24 Jul 07 05:28:23 PM PDT 24 24536660 ps
T601 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3314493999 Jul 07 05:28:31 PM PDT 24 Jul 07 05:28:47 PM PDT 24 3747836103 ps
T602 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1273204794 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:40 PM PDT 24 66945640 ps
T603 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1494804672 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:40 PM PDT 24 55870903 ps
T604 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2916530804 Jul 07 05:28:21 PM PDT 24 Jul 07 05:28:22 PM PDT 24 12730907 ps
T605 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2116917448 Jul 07 05:28:27 PM PDT 24 Jul 07 05:28:30 PM PDT 24 234057304 ps
T606 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2078533561 Jul 07 05:28:21 PM PDT 24 Jul 07 05:28:23 PM PDT 24 333598825 ps
T106 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2375164660 Jul 07 05:28:31 PM PDT 24 Jul 07 05:28:46 PM PDT 24 614756361 ps
T607 /workspace/coverage/cover_reg_top/41.hmac_intr_test.726366890 Jul 07 05:28:45 PM PDT 24 Jul 07 05:28:46 PM PDT 24 13801161 ps
T608 /workspace/coverage/cover_reg_top/25.hmac_intr_test.653774761 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:36 PM PDT 24 11399416 ps
T609 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2794032088 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:46 PM PDT 24 35645868 ps
T610 /workspace/coverage/cover_reg_top/43.hmac_intr_test.4283864570 Jul 07 05:28:47 PM PDT 24 Jul 07 05:28:48 PM PDT 24 50708051 ps
T107 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2931280242 Jul 07 05:28:22 PM PDT 24 Jul 07 05:28:23 PM PDT 24 124650884 ps
T108 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1957856076 Jul 07 05:28:12 PM PDT 24 Jul 07 05:28:16 PM PDT 24 156528901 ps
T109 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2958261877 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:39 PM PDT 24 35324169 ps
T611 /workspace/coverage/cover_reg_top/11.hmac_intr_test.668025237 Jul 07 05:28:38 PM PDT 24 Jul 07 05:28:40 PM PDT 24 12740100 ps
T111 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2325342914 Jul 07 05:28:32 PM PDT 24 Jul 07 05:28:33 PM PDT 24 16328528 ps
T612 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2234612138 Jul 07 05:28:27 PM PDT 24 Jul 07 05:28:29 PM PDT 24 42758996 ps
T110 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3041034582 Jul 07 05:28:25 PM PDT 24 Jul 07 05:28:27 PM PDT 24 22824107 ps
T131 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1449131641 Jul 07 05:28:38 PM PDT 24 Jul 07 05:28:44 PM PDT 24 125280704 ps
T613 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3064813514 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:39 PM PDT 24 49522151 ps
T614 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2202222916 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:36 PM PDT 24 214077504 ps
T615 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1626910703 Jul 07 05:28:18 PM PDT 24 Jul 07 05:28:21 PM PDT 24 746617245 ps
T616 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.429545153 Jul 07 05:28:23 PM PDT 24 Jul 07 05:28:28 PM PDT 24 132313067 ps
T617 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1448389449 Jul 07 05:28:14 PM PDT 24 Jul 07 05:28:16 PM PDT 24 44857455 ps
T130 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1701148955 Jul 07 05:28:26 PM PDT 24 Jul 07 05:28:30 PM PDT 24 622723274 ps
T618 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.37683997 Jul 07 05:28:34 PM PDT 24 Jul 07 05:28:36 PM PDT 24 48212923 ps
T619 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4009884190 Jul 07 05:28:49 PM PDT 24 Jul 07 05:28:51 PM PDT 24 263358173 ps
T620 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1493773489 Jul 07 05:28:17 PM PDT 24 Jul 07 05:28:18 PM PDT 24 72631187 ps
T112 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3696549436 Jul 07 05:28:32 PM PDT 24 Jul 07 05:28:34 PM PDT 24 109874097 ps
T621 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3113845543 Jul 07 05:28:31 PM PDT 24 Jul 07 05:28:38 PM PDT 24 61720271 ps
T622 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.553666153 Jul 07 05:28:31 PM PDT 24 Jul 07 05:28:33 PM PDT 24 24985896 ps
T623 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3347205450 Jul 07 05:28:50 PM PDT 24 Jul 07 05:28:53 PM PDT 24 84924897 ps
T624 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3132518513 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:43 PM PDT 24 47311250 ps
T625 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3331399013 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:40 PM PDT 24 12039571 ps
T626 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1787011983 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:38 PM PDT 24 42624420 ps
T627 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1451400033 Jul 07 05:28:26 PM PDT 24 Jul 07 05:28:27 PM PDT 24 53670659 ps
T628 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1361460372 Jul 07 05:28:49 PM PDT 24 Jul 07 05:28:50 PM PDT 24 15429059 ps
T629 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2821488937 Jul 07 05:28:15 PM PDT 24 Jul 07 05:28:19 PM PDT 24 124905813 ps
T630 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4147275703 Jul 07 05:28:29 PM PDT 24 Jul 07 05:28:31 PM PDT 24 64471401 ps
T631 /workspace/coverage/cover_reg_top/14.hmac_intr_test.133322571 Jul 07 05:28:22 PM PDT 24 Jul 07 05:28:23 PM PDT 24 40468290 ps
T632 /workspace/coverage/cover_reg_top/9.hmac_intr_test.4179378898 Jul 07 05:28:25 PM PDT 24 Jul 07 05:28:26 PM PDT 24 16566832 ps
T633 /workspace/coverage/cover_reg_top/32.hmac_intr_test.129566262 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:39 PM PDT 24 13964077 ps
T634 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3605120003 Jul 07 05:28:18 PM PDT 24 Jul 07 05:28:23 PM PDT 24 481704947 ps
T113 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.88997807 Jul 07 05:28:15 PM PDT 24 Jul 07 05:28:24 PM PDT 24 302450941 ps
T635 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1752526682 Jul 07 05:28:38 PM PDT 24 Jul 07 05:28:40 PM PDT 24 19195720 ps
T636 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2449217244 Jul 07 05:28:24 PM PDT 24 Jul 07 05:28:26 PM PDT 24 111186742 ps
T637 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1798659436 Jul 07 05:28:28 PM PDT 24 Jul 07 05:28:31 PM PDT 24 257634788 ps
T638 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3018782328 Jul 07 05:28:26 PM PDT 24 Jul 07 05:28:28 PM PDT 24 23353418 ps
T639 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4116515748 Jul 07 05:28:44 PM PDT 24 Jul 07 05:28:46 PM PDT 24 442945258 ps
T640 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3940175725 Jul 07 05:28:45 PM PDT 24 Jul 07 05:28:46 PM PDT 24 60296944 ps
T641 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2205401050 Jul 07 05:28:50 PM PDT 24 Jul 07 05:28:51 PM PDT 24 12764186 ps
T642 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1375331219 Jul 07 05:28:29 PM PDT 24 Jul 07 05:28:31 PM PDT 24 82488330 ps
T643 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2033813439 Jul 07 05:28:43 PM PDT 24 Jul 07 05:28:44 PM PDT 24 31586029 ps
T644 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4176875929 Jul 07 05:28:51 PM PDT 24 Jul 07 05:28:53 PM PDT 24 59913832 ps
T645 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1818154296 Jul 07 05:29:01 PM PDT 24 Jul 07 05:29:02 PM PDT 24 42173365 ps
T646 /workspace/coverage/cover_reg_top/36.hmac_intr_test.4232559574 Jul 07 05:28:45 PM PDT 24 Jul 07 05:28:46 PM PDT 24 32332952 ps
T647 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3005021952 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:38 PM PDT 24 16391363 ps
T648 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2405776115 Jul 07 05:28:26 PM PDT 24 Jul 07 05:28:27 PM PDT 24 13498987 ps
T649 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2148655565 Jul 07 05:28:36 PM PDT 24 Jul 07 05:28:38 PM PDT 24 127036278 ps
T650 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3730125523 Jul 07 05:28:53 PM PDT 24 Jul 07 05:28:54 PM PDT 24 27810748 ps
T651 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3586293612 Jul 07 05:28:34 PM PDT 24 Jul 07 05:28:38 PM PDT 24 68331868 ps
T652 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2143978848 Jul 07 05:28:37 PM PDT 24 Jul 07 05:28:40 PM PDT 24 420584943 ps
T653 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2292966957 Jul 07 05:28:50 PM PDT 24 Jul 07 05:28:53 PM PDT 24 459909151 ps
T654 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3063789803 Jul 07 05:28:44 PM PDT 24 Jul 07 05:28:47 PM PDT 24 1891416579 ps
T655 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2249691532 Jul 07 05:28:35 PM PDT 24 Jul 07 05:28:36 PM PDT 24 32702225 ps
T656 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3180465806 Jul 07 05:28:18 PM PDT 24 Jul 07 05:28:28 PM PDT 24 898416350 ps
T657 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2348041928 Jul 07 05:28:42 PM PDT 24 Jul 07 05:28:44 PM PDT 24 29504778 ps
T658 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1136751742 Jul 07 05:28:29 PM PDT 24 Jul 07 05:28:33 PM PDT 24 180335275 ps

Test location /workspace/coverage/default/46.hmac_long_msg.566985022
Short name T4
Test name
Test status
Simulation time 7489482265 ps
CPU time 134.62 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:34:13 PM PDT 24
Peak memory 216684 kb
Host smart-7ec05fe5-2025-4d67-9863-6e59e2401e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566985022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.566985022
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3831332305
Short name T15
Test name
Test status
Simulation time 5473261773 ps
CPU time 1064.16 seconds
Started Jul 07 05:32:01 PM PDT 24
Finished Jul 07 05:49:46 PM PDT 24
Peak memory 760904 kb
Host smart-9f692a34-bb80-4e9a-b681-067bc27987a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831332305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3831332305
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2400682499
Short name T23
Test name
Test status
Simulation time 71754668226 ps
CPU time 1673.83 seconds
Started Jul 07 05:31:12 PM PDT 24
Finished Jul 07 05:59:07 PM PDT 24
Peak memory 747224 kb
Host smart-d7c26170-33d6-417b-b2fb-a9417afaa229
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400682499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2400682499
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1438659265
Short name T30
Test name
Test status
Simulation time 946528892 ps
CPU time 46.67 seconds
Started Jul 07 05:31:36 PM PDT 24
Finished Jul 07 05:32:23 PM PDT 24
Peak memory 200384 kb
Host smart-b7f463a7-e40f-4835-9423-4347261336db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438659265 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1438659265
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2881561652
Short name T18
Test name
Test status
Simulation time 54056269416 ps
CPU time 305.72 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 454960 kb
Host smart-c91bd8e5-70b1-4ab7-87f5-03c33c9ee48e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881561652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2881561652
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_stress_all.4119585074
Short name T61
Test name
Test status
Simulation time 22892601441 ps
CPU time 1917.85 seconds
Started Jul 07 05:31:09 PM PDT 24
Finished Jul 07 06:03:08 PM PDT 24
Peak memory 716472 kb
Host smart-38b8ade1-8bf4-4e5f-97bb-080ab47d1f43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119585074 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4119585074
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3732525684
Short name T74
Test name
Test status
Simulation time 136359466 ps
CPU time 4.12 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:36 PM PDT 24
Peak memory 200328 kb
Host smart-c97259e6-d4c6-49be-a369-1486759ba182
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732525684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3732525684
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.2190157402
Short name T35
Test name
Test status
Simulation time 100014517647 ps
CPU time 5355.11 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 07:00:06 PM PDT 24
Peak memory 807836 kb
Host smart-5a80e52c-84dc-4403-8016-413dbd813f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190157402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2190157402
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3877953341
Short name T62
Test name
Test status
Simulation time 33043392 ps
CPU time 0.82 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:31:06 PM PDT 24
Peak memory 218272 kb
Host smart-a696db1f-e8ac-4480-a80a-374807a42227
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877953341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3877953341
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/15.hmac_error.3472198048
Short name T2
Test name
Test status
Simulation time 10517788006 ps
CPU time 145.4 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:33:36 PM PDT 24
Peak memory 200332 kb
Host smart-72feb8ea-4e8b-4fec-ad28-0bbbf601a0f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472198048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3472198048
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1218109733
Short name T102
Test name
Test status
Simulation time 28503365 ps
CPU time 0.9 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 200152 kb
Host smart-83a86ad6-9f8c-4c80-bfcb-a1b3d1c7660a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218109733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1218109733
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1560129958
Short name T34
Test name
Test status
Simulation time 182945056435 ps
CPU time 1458.17 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:55:30 PM PDT 24
Peak memory 768008 kb
Host smart-496bebd5-95ac-427c-a875-f574ad450f97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560129958 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1560129958
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1768869601
Short name T76
Test name
Test status
Simulation time 902314544 ps
CPU time 4.31 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:42 PM PDT 24
Peak memory 200248 kb
Host smart-c53dadb3-ea33-4499-a86f-0018d0e9084b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768869601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1768869601
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/23.hmac_stress_all.678331382
Short name T81
Test name
Test status
Simulation time 370200215206 ps
CPU time 2021.87 seconds
Started Jul 07 05:31:13 PM PDT 24
Finished Jul 07 06:04:55 PM PDT 24
Peak memory 714424 kb
Host smart-c2c6c30a-c049-49b8-a1cc-60359c1fa215
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678331382 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.678331382
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_alert_test.4209937958
Short name T180
Test name
Test status
Simulation time 33681639 ps
CPU time 0.6 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:31:11 PM PDT 24
Peak memory 195812 kb
Host smart-fec73623-4839-4881-b29f-aba44bd2ab43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209937958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.4209937958
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.384229213
Short name T55
Test name
Test status
Simulation time 101386897 ps
CPU time 5.4 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:30:56 PM PDT 24
Peak memory 200196 kb
Host smart-614f7385-084a-49cd-a15c-47605db131f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384229213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.384229213
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2449217244
Short name T636
Test name
Test status
Simulation time 111186742 ps
CPU time 1.93 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:26 PM PDT 24
Peak memory 200296 kb
Host smart-87b1f97f-7f6d-4de1-be29-6ccff74f3581
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449217244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2449217244
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1957856076
Short name T108
Test name
Test status
Simulation time 156528901 ps
CPU time 3.33 seconds
Started Jul 07 05:28:12 PM PDT 24
Finished Jul 07 05:28:16 PM PDT 24
Peak memory 200188 kb
Host smart-7b686eee-4db2-46a3-9613-d406832c600b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957856076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1957856076
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2375164660
Short name T106
Test name
Test status
Simulation time 614756361 ps
CPU time 14.06 seconds
Started Jul 07 05:28:31 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 200324 kb
Host smart-9a5e50e7-a708-4bb6-a556-c988c6d12299
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375164660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2375164660
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3113845543
Short name T621
Test name
Test status
Simulation time 61720271 ps
CPU time 0.93 seconds
Started Jul 07 05:28:31 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 200080 kb
Host smart-0a65decd-df61-4f32-8b6b-7886cf600432
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113845543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3113845543
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2234612138
Short name T612
Test name
Test status
Simulation time 42758996 ps
CPU time 1.33 seconds
Started Jul 07 05:28:27 PM PDT 24
Finished Jul 07 05:28:29 PM PDT 24
Peak memory 200260 kb
Host smart-b6f9dc42-2a56-4b9a-b6be-707833fd60f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234612138 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2234612138
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1901112631
Short name T101
Test name
Test status
Simulation time 26552159 ps
CPU time 0.83 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:25 PM PDT 24
Peak memory 199884 kb
Host smart-20de05c3-2f40-4903-8557-34564158be7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901112631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1901112631
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1493773489
Short name T620
Test name
Test status
Simulation time 72631187 ps
CPU time 0.64 seconds
Started Jul 07 05:28:17 PM PDT 24
Finished Jul 07 05:28:18 PM PDT 24
Peak memory 195184 kb
Host smart-cb2b0b47-c402-403b-9139-f46a549228aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493773489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1493773489
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1448389449
Short name T617
Test name
Test status
Simulation time 44857455 ps
CPU time 1.9 seconds
Started Jul 07 05:28:14 PM PDT 24
Finished Jul 07 05:28:16 PM PDT 24
Peak memory 200284 kb
Host smart-48167621-a837-49cc-ac77-6a51e0b96f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448389449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1448389449
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.4147305800
Short name T535
Test name
Test status
Simulation time 72211806 ps
CPU time 3.86 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:37 PM PDT 24
Peak memory 200264 kb
Host smart-da38a497-784c-4860-83e3-9864f8e9c890
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147305800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.4147305800
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.88997807
Short name T113
Test name
Test status
Simulation time 302450941 ps
CPU time 8 seconds
Started Jul 07 05:28:15 PM PDT 24
Finished Jul 07 05:28:24 PM PDT 24
Peak memory 200280 kb
Host smart-66a19bc4-478c-41a2-9e95-6ba6352f1244
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88997807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.88997807
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2164840854
Short name T553
Test name
Test status
Simulation time 618877968 ps
CPU time 14 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 200160 kb
Host smart-757add68-ffca-4557-a6be-75283935ed36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164840854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2164840854
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3041034582
Short name T110
Test name
Test status
Simulation time 22824107 ps
CPU time 1 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:27 PM PDT 24
Peak memory 199904 kb
Host smart-e741a0c4-d2b2-42df-9e92-ebcf12101307
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041034582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3041034582
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1039078833
Short name T544
Test name
Test status
Simulation time 93137948 ps
CPU time 1.61 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 200272 kb
Host smart-116bdece-5360-4894-afac-8323cb85bf14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039078833 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1039078833
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2325342914
Short name T111
Test name
Test status
Simulation time 16328528 ps
CPU time 0.8 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:33 PM PDT 24
Peak memory 200124 kb
Host smart-68273611-60c9-4596-807b-ecc0f3483105
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325342914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2325342914
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.998413548
Short name T596
Test name
Test status
Simulation time 26115192 ps
CPU time 0.57 seconds
Started Jul 07 05:28:21 PM PDT 24
Finished Jul 07 05:28:22 PM PDT 24
Peak memory 195168 kb
Host smart-1b91417c-6664-4f87-bb76-c525d6e1566a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998413548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.998413548
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3161175627
Short name T587
Test name
Test status
Simulation time 184283430 ps
CPU time 1.19 seconds
Started Jul 07 05:28:29 PM PDT 24
Finished Jul 07 05:28:31 PM PDT 24
Peak memory 200284 kb
Host smart-eca0a36e-2d51-461d-9291-53e606a9ad6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161175627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3161175627
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.553666153
Short name T622
Test name
Test status
Simulation time 24985896 ps
CPU time 1.24 seconds
Started Jul 07 05:28:31 PM PDT 24
Finished Jul 07 05:28:33 PM PDT 24
Peak memory 200264 kb
Host smart-7ef6221c-9746-4303-838f-8bc7fcef787c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553666153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.553666153
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1084110906
Short name T132
Test name
Test status
Simulation time 500223920 ps
CPU time 3.98 seconds
Started Jul 07 05:28:17 PM PDT 24
Finished Jul 07 05:28:21 PM PDT 24
Peak memory 200316 kb
Host smart-5a8ab524-c974-49b6-bcc5-12827e82ce35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084110906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1084110906
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1273204794
Short name T602
Test name
Test status
Simulation time 66945640 ps
CPU time 1.72 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 200368 kb
Host smart-d502d8e0-843c-4b73-a524-16efb26ef5f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273204794 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1273204794
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.892538303
Short name T541
Test name
Test status
Simulation time 19797475 ps
CPU time 0.69 seconds
Started Jul 07 05:28:28 PM PDT 24
Finished Jul 07 05:28:29 PM PDT 24
Peak memory 198180 kb
Host smart-f10f6390-93fc-481b-b6a0-9340b8364921
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892538303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.892538303
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.64424745
Short name T537
Test name
Test status
Simulation time 17079834 ps
CPU time 0.61 seconds
Started Jul 07 05:28:34 PM PDT 24
Finished Jul 07 05:28:35 PM PDT 24
Peak memory 195248 kb
Host smart-2dc965e6-c81c-4036-ae57-277560060b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64424745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.64424745
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2078533561
Short name T606
Test name
Test status
Simulation time 333598825 ps
CPU time 1.84 seconds
Started Jul 07 05:28:21 PM PDT 24
Finished Jul 07 05:28:23 PM PDT 24
Peak memory 199972 kb
Host smart-894fbe07-98cf-4ecd-90af-06bac41fd93d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078533561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2078533561
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2348041928
Short name T657
Test name
Test status
Simulation time 29504778 ps
CPU time 1.34 seconds
Started Jul 07 05:28:42 PM PDT 24
Finished Jul 07 05:28:44 PM PDT 24
Peak memory 200320 kb
Host smart-1cb94395-8d08-4656-b738-6d514b8b5637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348041928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2348041928
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.804816467
Short name T581
Test name
Test status
Simulation time 96405327 ps
CPU time 2.27 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:26 PM PDT 24
Peak memory 200312 kb
Host smart-b9c75e92-6ac5-45ad-8ff9-36e748ff7aa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804816467 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.804816467
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2202222916
Short name T614
Test name
Test status
Simulation time 214077504 ps
CPU time 0.89 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:36 PM PDT 24
Peak memory 199780 kb
Host smart-24578c51-1709-4b9a-b946-11056a927728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202222916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2202222916
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.668025237
Short name T611
Test name
Test status
Simulation time 12740100 ps
CPU time 0.64 seconds
Started Jul 07 05:28:38 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 195304 kb
Host smart-26dfade6-98d3-4c02-b8ae-4dd14b970874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668025237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.668025237
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.233808838
Short name T563
Test name
Test status
Simulation time 41602080 ps
CPU time 1.68 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:34 PM PDT 24
Peak memory 200304 kb
Host smart-aefe7f0c-beb1-42de-9e34-d5f1e2373e3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233808838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.233808838
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2138661034
Short name T566
Test name
Test status
Simulation time 703073053 ps
CPU time 3.42 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:42 PM PDT 24
Peak memory 200276 kb
Host smart-a86793a0-93cb-4748-b001-802f07ef1c12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138661034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2138661034
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3944807092
Short name T127
Test name
Test status
Simulation time 220888205 ps
CPU time 4.15 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 200252 kb
Host smart-cf96b886-56ed-4820-9668-a0489c0ba03f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944807092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3944807092
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3611930793
Short name T539
Test name
Test status
Simulation time 210998712 ps
CPU time 1.11 seconds
Started Jul 07 05:28:38 PM PDT 24
Finished Jul 07 05:28:41 PM PDT 24
Peak memory 200136 kb
Host smart-fb50a6b8-5d2e-4176-bac9-630585f88663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611930793 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3611930793
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2405776115
Short name T648
Test name
Test status
Simulation time 13498987 ps
CPU time 0.55 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:27 PM PDT 24
Peak memory 195160 kb
Host smart-f5588bc3-5f92-42ee-8124-b90d46dd2022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405776115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2405776115
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2143978848
Short name T652
Test name
Test status
Simulation time 420584943 ps
CPU time 1.11 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 200068 kb
Host smart-cba38026-8ce3-4c88-b9e8-cb493d3a7e17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143978848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2143978848
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1607823322
Short name T577
Test name
Test status
Simulation time 218144156 ps
CPU time 3.28 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 200276 kb
Host smart-df860ef4-ab9d-4b3c-aecc-57503cd4c554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607823322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1607823322
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.72113919
Short name T124
Test name
Test status
Simulation time 3091641889 ps
CPU time 4.13 seconds
Started Jul 07 05:28:34 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 200408 kb
Host smart-c4c19933-a4e0-4575-8a8a-eee1ac2b2b88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72113919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.72113919
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2704480338
Short name T600
Test name
Test status
Simulation time 24536660 ps
CPU time 1.34 seconds
Started Jul 07 05:28:22 PM PDT 24
Finished Jul 07 05:28:23 PM PDT 24
Peak memory 200260 kb
Host smart-7d2fc001-0612-4452-9ac0-1dfa53df0a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704480338 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2704480338
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3737808170
Short name T565
Test name
Test status
Simulation time 143303708 ps
CPU time 1.06 seconds
Started Jul 07 05:28:28 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 200128 kb
Host smart-117f1a89-e12e-4981-9381-4b9decd84178
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737808170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3737808170
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3543534133
Short name T569
Test name
Test status
Simulation time 38290311 ps
CPU time 0.58 seconds
Started Jul 07 05:28:30 PM PDT 24
Finished Jul 07 05:28:31 PM PDT 24
Peak memory 195176 kb
Host smart-67d4eb38-e1ee-40db-a59e-2f8bd7bf9460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543534133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3543534133
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2330965985
Short name T570
Test name
Test status
Simulation time 203255546 ps
CPU time 1.69 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:41 PM PDT 24
Peak memory 200160 kb
Host smart-50ff9319-5f97-4815-9f5c-6672a8eae9c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330965985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2330965985
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1289030805
Short name T536
Test name
Test status
Simulation time 76693086 ps
CPU time 1.23 seconds
Started Jul 07 05:28:40 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 200212 kb
Host smart-a46e07c1-42b0-4e11-bccb-0679cb6ede43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289030805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1289030805
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3347205450
Short name T623
Test name
Test status
Simulation time 84924897 ps
CPU time 1.86 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:28:53 PM PDT 24
Peak memory 200344 kb
Host smart-55b8484e-4814-4c9b-9542-e506c44aaac2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347205450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3347205450
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.695571560
Short name T594
Test name
Test status
Simulation time 247960463 ps
CPU time 1.98 seconds
Started Jul 07 05:28:13 PM PDT 24
Finished Jul 07 05:28:15 PM PDT 24
Peak memory 200268 kb
Host smart-62ab5b57-cda6-4784-9598-757f7695da6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695571560 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.695571560
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1139645771
Short name T100
Test name
Test status
Simulation time 33460352 ps
CPU time 0.98 seconds
Started Jul 07 05:28:28 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 199556 kb
Host smart-190863f4-ddf9-4ccf-9df5-800b985aabb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139645771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1139645771
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.133322571
Short name T631
Test name
Test status
Simulation time 40468290 ps
CPU time 0.62 seconds
Started Jul 07 05:28:22 PM PDT 24
Finished Jul 07 05:28:23 PM PDT 24
Peak memory 195272 kb
Host smart-111dc924-cb28-4cc4-b11d-91cc6b83bd93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133322571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.133322571
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3024032756
Short name T118
Test name
Test status
Simulation time 209916856 ps
CPU time 2.05 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 200280 kb
Host smart-93c755e3-fff5-4055-9a8c-57c0462f539a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024032756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3024032756
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2797952149
Short name T567
Test name
Test status
Simulation time 43172782 ps
CPU time 1.35 seconds
Started Jul 07 05:28:47 PM PDT 24
Finished Jul 07 05:28:48 PM PDT 24
Peak memory 200264 kb
Host smart-80a24f87-c0e7-4009-b4f5-905c546c6d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797952149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2797952149
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3064813514
Short name T613
Test name
Test status
Simulation time 49522151 ps
CPU time 3 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 200336 kb
Host smart-d4f6a8ac-c75c-497b-84ac-a4e43a8ff1a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064813514 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3064813514
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2931280242
Short name T107
Test name
Test status
Simulation time 124650884 ps
CPU time 0.92 seconds
Started Jul 07 05:28:22 PM PDT 24
Finished Jul 07 05:28:23 PM PDT 24
Peak memory 199940 kb
Host smart-ff26e621-febc-4fbf-b33d-497adf79c2a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931280242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2931280242
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1752526682
Short name T635
Test name
Test status
Simulation time 19195720 ps
CPU time 0.58 seconds
Started Jul 07 05:28:38 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 195320 kb
Host smart-fccfb822-c40e-4bad-9d9d-05aff3b24104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752526682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1752526682
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2138222663
Short name T117
Test name
Test status
Simulation time 64640965 ps
CPU time 1.67 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 200332 kb
Host smart-cc6ef2b1-7cf4-4d70-9bab-0076e8af64fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138222663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2138222663
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4009884190
Short name T619
Test name
Test status
Simulation time 263358173 ps
CPU time 2.51 seconds
Started Jul 07 05:28:49 PM PDT 24
Finished Jul 07 05:28:51 PM PDT 24
Peak memory 200272 kb
Host smart-b90f2d81-f25e-4dc2-96a8-45f535f54f35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009884190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.4009884190
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1449131641
Short name T131
Test name
Test status
Simulation time 125280704 ps
CPU time 3.98 seconds
Started Jul 07 05:28:38 PM PDT 24
Finished Jul 07 05:28:44 PM PDT 24
Peak memory 200312 kb
Host smart-8a6aaa62-c8b4-4f1e-b822-7cdad790c3c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449131641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1449131641
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3339428950
Short name T546
Test name
Test status
Simulation time 94491452 ps
CPU time 2.37 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:44 PM PDT 24
Peak memory 200344 kb
Host smart-5f90e261-5b1d-4a86-9168-6b8085c5fb9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339428950 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3339428950
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3249302028
Short name T579
Test name
Test status
Simulation time 41831005 ps
CPU time 0.72 seconds
Started Jul 07 05:28:27 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 197768 kb
Host smart-a44cf1e2-b4b7-4244-acb4-902cbc565d52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249302028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3249302028
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3331399013
Short name T625
Test name
Test status
Simulation time 12039571 ps
CPU time 0.56 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 195172 kb
Host smart-b79ca13e-da2c-4345-9c7f-8cf1a67fd54f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331399013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3331399013
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1319682391
Short name T119
Test name
Test status
Simulation time 132562563 ps
CPU time 2.22 seconds
Started Jul 07 05:28:49 PM PDT 24
Finished Jul 07 05:28:51 PM PDT 24
Peak memory 200256 kb
Host smart-2e8fd013-af14-4297-a4c1-2a0191f63460
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319682391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1319682391
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2821488937
Short name T629
Test name
Test status
Simulation time 124905813 ps
CPU time 3.59 seconds
Started Jul 07 05:28:15 PM PDT 24
Finished Jul 07 05:28:19 PM PDT 24
Peak memory 200292 kb
Host smart-8eed7205-34db-499e-9533-d665bea51cb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821488937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2821488937
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1701148955
Short name T130
Test name
Test status
Simulation time 622723274 ps
CPU time 3.25 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 200548 kb
Host smart-5c1332fc-b020-4537-94c2-a89bab1e23b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701148955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1701148955
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4008557923
Short name T547
Test name
Test status
Simulation time 300903620 ps
CPU time 1.76 seconds
Started Jul 07 05:28:13 PM PDT 24
Finished Jul 07 05:28:16 PM PDT 24
Peak memory 200368 kb
Host smart-41009713-7178-4e8f-8657-857d9f8fdb40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008557923 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4008557923
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2597269880
Short name T598
Test name
Test status
Simulation time 67352790 ps
CPU time 0.71 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:28:58 PM PDT 24
Peak memory 197940 kb
Host smart-96ea31b8-a1c6-4f5b-8c92-bfb1967a3020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597269880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2597269880
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1248632978
Short name T534
Test name
Test status
Simulation time 15759194 ps
CPU time 0.56 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 195144 kb
Host smart-35cbb516-7573-4b0c-a789-8177585ef2bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248632978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1248632978
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4116515748
Short name T639
Test name
Test status
Simulation time 442945258 ps
CPU time 1.71 seconds
Started Jul 07 05:28:44 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 200284 kb
Host smart-969f5941-ec84-4e61-9148-804cd67f3b79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116515748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4116515748
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.710752033
Short name T540
Test name
Test status
Simulation time 215835651 ps
CPU time 2.24 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 200272 kb
Host smart-e88c6958-de8b-4590-a590-504d31d7aea5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710752033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.710752033
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.766504240
Short name T129
Test name
Test status
Simulation time 50586952 ps
CPU time 1.7 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 200268 kb
Host smart-1dff1587-9eed-4946-8a7a-c089bd8c0cda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766504240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.766504240
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2342232227
Short name T558
Test name
Test status
Simulation time 278721319 ps
CPU time 1.25 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:37 PM PDT 24
Peak memory 200260 kb
Host smart-c2870fab-28db-4c04-87ea-7772e648e868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342232227 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2342232227
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3005021952
Short name T647
Test name
Test status
Simulation time 16391363 ps
CPU time 0.91 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 200108 kb
Host smart-af3e8540-e9d5-4bb2-b639-b2b7714776b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005021952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3005021952
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2949463735
Short name T582
Test name
Test status
Simulation time 14355105 ps
CPU time 0.56 seconds
Started Jul 07 05:28:56 PM PDT 24
Finished Jul 07 05:28:57 PM PDT 24
Peak memory 195120 kb
Host smart-b679a3f5-c61f-4a1b-8e59-fc2d3b8dd2e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949463735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2949463735
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3426059508
Short name T115
Test name
Test status
Simulation time 304261105 ps
CPU time 1.74 seconds
Started Jul 07 05:28:40 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 200552 kb
Host smart-2fe51c36-7220-4066-b19e-604e44365924
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426059508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3426059508
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.381027620
Short name T528
Test name
Test status
Simulation time 216071890 ps
CPU time 3.82 seconds
Started Jul 07 05:28:42 PM PDT 24
Finished Jul 07 05:28:47 PM PDT 24
Peak memory 200284 kb
Host smart-ba8ff4b9-0a73-4a11-b44a-d94e440393e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381027620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.381027620
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3063789803
Short name T654
Test name
Test status
Simulation time 1891416579 ps
CPU time 2.98 seconds
Started Jul 07 05:28:44 PM PDT 24
Finished Jul 07 05:28:47 PM PDT 24
Peak memory 200332 kb
Host smart-a3797ec5-18e8-4055-a011-dca5a02b5746
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063789803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3063789803
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3524447884
Short name T530
Test name
Test status
Simulation time 607738548 ps
CPU time 3.05 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 208644 kb
Host smart-fcbae274-552b-4435-bf0f-b4a2fceb828b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524447884 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3524447884
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1787011983
Short name T626
Test name
Test status
Simulation time 42624420 ps
CPU time 0.67 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 198148 kb
Host smart-938db4c7-efe2-4ac3-befa-c39cd4d7165f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787011983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1787011983
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3940175725
Short name T640
Test name
Test status
Simulation time 60296944 ps
CPU time 0.61 seconds
Started Jul 07 05:28:45 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 195268 kb
Host smart-8a066dd8-eb57-4bdb-bbc8-3c20b4121ce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940175725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3940175725
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2148655565
Short name T649
Test name
Test status
Simulation time 127036278 ps
CPU time 1.17 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 199744 kb
Host smart-0ef1cf4d-667c-4a03-b4af-870382f0fd24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148655565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2148655565
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1798659436
Short name T637
Test name
Test status
Simulation time 257634788 ps
CPU time 3.34 seconds
Started Jul 07 05:28:28 PM PDT 24
Finished Jul 07 05:28:31 PM PDT 24
Peak memory 200304 kb
Host smart-8107fb2d-12dd-4f09-9999-8074a3967154
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798659436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1798659436
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3706185269
Short name T128
Test name
Test status
Simulation time 877666502 ps
CPU time 4.24 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:45 PM PDT 24
Peak memory 200304 kb
Host smart-04b20a4d-4cf4-412f-8fdb-4427fd74ce74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706185269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3706185269
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1136751742
Short name T658
Test name
Test status
Simulation time 180335275 ps
CPU time 3.28 seconds
Started Jul 07 05:28:29 PM PDT 24
Finished Jul 07 05:28:33 PM PDT 24
Peak memory 200116 kb
Host smart-8afa48ec-9e18-4eb4-8461-c63eb2c3ed00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136751742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1136751742
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3180465806
Short name T656
Test name
Test status
Simulation time 898416350 ps
CPU time 10.03 seconds
Started Jul 07 05:28:18 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 200212 kb
Host smart-33b5dd3e-6ca9-4901-b019-17f3b6c3f1fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180465806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3180465806
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1956728854
Short name T549
Test name
Test status
Simulation time 26056597 ps
CPU time 0.85 seconds
Started Jul 07 05:28:18 PM PDT 24
Finished Jul 07 05:28:19 PM PDT 24
Peak memory 199736 kb
Host smart-570609db-a40a-4979-b339-7e3d64863424
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956728854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1956728854
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.793477930
Short name T597
Test name
Test status
Simulation time 1923765564 ps
CPU time 2.34 seconds
Started Jul 07 05:28:19 PM PDT 24
Finished Jul 07 05:28:22 PM PDT 24
Peak memory 200312 kb
Host smart-7d9d17a1-7719-4304-a557-d2664f7daf39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793477930 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.793477930
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2060451962
Short name T105
Test name
Test status
Simulation time 36902575 ps
CPU time 0.82 seconds
Started Jul 07 05:28:29 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 199612 kb
Host smart-ffe62be9-38cc-4a1a-937a-f507d20a4eea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060451962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2060451962
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.43666349
Short name T548
Test name
Test status
Simulation time 30385085 ps
CPU time 0.61 seconds
Started Jul 07 05:28:13 PM PDT 24
Finished Jul 07 05:28:14 PM PDT 24
Peak memory 195204 kb
Host smart-e68ed4fc-c955-4b0e-b72f-9879e3682876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43666349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.43666349
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2794347101
Short name T564
Test name
Test status
Simulation time 21766264 ps
CPU time 1.08 seconds
Started Jul 07 05:28:18 PM PDT 24
Finished Jul 07 05:28:20 PM PDT 24
Peak memory 200244 kb
Host smart-a7e85c58-2153-4d23-8389-d087c23116ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794347101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2794347101
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1952588390
Short name T555
Test name
Test status
Simulation time 311015715 ps
CPU time 4.2 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 200292 kb
Host smart-1bc426fc-e44b-4322-98c2-36bab7a09460
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952588390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1952588390
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.4034940972
Short name T126
Test name
Test status
Simulation time 174848635 ps
CPU time 2.89 seconds
Started Jul 07 05:28:27 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 200360 kb
Host smart-0c3df6e8-4d8c-4ace-8e48-f92d13ff10db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034940972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.4034940972
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2628345543
Short name T599
Test name
Test status
Simulation time 20037919 ps
CPU time 0.59 seconds
Started Jul 07 05:28:33 PM PDT 24
Finished Jul 07 05:28:35 PM PDT 24
Peak memory 195228 kb
Host smart-110ec054-f265-4fa5-9157-2af5d7e8fbd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628345543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2628345543
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2249691532
Short name T655
Test name
Test status
Simulation time 32702225 ps
CPU time 0.61 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:36 PM PDT 24
Peak memory 195176 kb
Host smart-4ec432f6-6b01-4d76-8c22-78081837da4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249691532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2249691532
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2916530804
Short name T604
Test name
Test status
Simulation time 12730907 ps
CPU time 0.6 seconds
Started Jul 07 05:28:21 PM PDT 24
Finished Jul 07 05:28:22 PM PDT 24
Peak memory 194884 kb
Host smart-d2622c32-caa1-47d1-a0f4-3cc10cad4fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916530804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2916530804
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2718486246
Short name T576
Test name
Test status
Simulation time 40265041 ps
CPU time 0.6 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 195196 kb
Host smart-ddee4880-2b5d-464c-9e57-246e21fa15b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718486246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2718486246
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3132518513
Short name T624
Test name
Test status
Simulation time 47311250 ps
CPU time 0.61 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 195140 kb
Host smart-fd521943-4910-4e82-b460-9bdeebd15aa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132518513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3132518513
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.653774761
Short name T608
Test name
Test status
Simulation time 11399416 ps
CPU time 0.6 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:36 PM PDT 24
Peak memory 195332 kb
Host smart-e1f13acc-018e-451d-8f9d-aed804d05f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653774761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.653774761
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3277460108
Short name T591
Test name
Test status
Simulation time 38139587 ps
CPU time 0.62 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 195288 kb
Host smart-3e75d054-1a24-4b41-bce4-c459ebf90785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277460108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3277460108
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2205401050
Short name T641
Test name
Test status
Simulation time 12764186 ps
CPU time 0.6 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:28:51 PM PDT 24
Peak memory 195212 kb
Host smart-7365f7fc-0b43-439a-ac90-6e5baf44afae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205401050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2205401050
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2966288317
Short name T538
Test name
Test status
Simulation time 37036040 ps
CPU time 0.58 seconds
Started Jul 07 05:28:42 PM PDT 24
Finished Jul 07 05:28:44 PM PDT 24
Peak memory 195140 kb
Host smart-335fb1aa-9948-4c3a-a588-bb0263f6c95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966288317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2966288317
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2692335031
Short name T552
Test name
Test status
Simulation time 51122054 ps
CPU time 0.6 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:28:56 PM PDT 24
Peak memory 195164 kb
Host smart-c77d858a-fee0-48cc-9743-f6a9f54aa551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692335031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2692335031
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4028574969
Short name T562
Test name
Test status
Simulation time 428151426 ps
CPU time 6.25 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:31 PM PDT 24
Peak memory 200080 kb
Host smart-086dff3c-6dd5-420f-83e3-a0fbddf1ec4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028574969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4028574969
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.429545153
Short name T616
Test name
Test status
Simulation time 132313067 ps
CPU time 5.33 seconds
Started Jul 07 05:28:23 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 199568 kb
Host smart-60497c1e-05c0-4a58-8d88-a6232087fff5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429545153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.429545153
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1451400033
Short name T627
Test name
Test status
Simulation time 53670659 ps
CPU time 0.87 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:27 PM PDT 24
Peak memory 199272 kb
Host smart-adc26833-8e1e-41ab-aacf-a9bfc681946e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451400033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1451400033
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1122150362
Short name T542
Test name
Test status
Simulation time 90763120 ps
CPU time 2.58 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:29 PM PDT 24
Peak memory 199836 kb
Host smart-5b035342-5a66-40e3-97e4-d3ee0e3d153b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122150362 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1122150362
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3018782328
Short name T638
Test name
Test status
Simulation time 23353418 ps
CPU time 0.81 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:28 PM PDT 24
Peak memory 199276 kb
Host smart-6dc7d7f2-92ef-4cf3-945c-994f596a466c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018782328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3018782328
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1375331219
Short name T642
Test name
Test status
Simulation time 82488330 ps
CPU time 0.6 seconds
Started Jul 07 05:28:29 PM PDT 24
Finished Jul 07 05:28:31 PM PDT 24
Peak memory 195200 kb
Host smart-f6427276-f80e-4db0-a628-032e03c786bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375331219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1375331219
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2116917448
Short name T605
Test name
Test status
Simulation time 234057304 ps
CPU time 2.22 seconds
Started Jul 07 05:28:27 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 200160 kb
Host smart-cf745656-d250-4b0b-8f54-d44be63f2414
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116917448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2116917448
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1662867340
Short name T551
Test name
Test status
Simulation time 102990563 ps
CPU time 1.44 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:26 PM PDT 24
Peak memory 200288 kb
Host smart-a965d18f-eda8-4502-addb-f5e833ebc2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662867340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1662867340
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.4128929337
Short name T125
Test name
Test status
Simulation time 467255369 ps
CPU time 3.74 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 200288 kb
Host smart-34725513-1cf4-4544-80df-e7ea5d9c78c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128929337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.4128929337
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.365830077
Short name T580
Test name
Test status
Simulation time 14760807 ps
CPU time 0.58 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:36 PM PDT 24
Peak memory 195308 kb
Host smart-8677a2ae-1916-45c5-81a5-ce793bb96ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365830077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.365830077
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1494804672
Short name T603
Test name
Test status
Simulation time 55870903 ps
CPU time 0.59 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 195228 kb
Host smart-8c208049-f72a-4e1e-8667-e315bf210895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494804672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1494804672
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.129566262
Short name T633
Test name
Test status
Simulation time 13964077 ps
CPU time 0.6 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 195224 kb
Host smart-61297e99-bae0-4e69-bc06-af5a5331e3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129566262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.129566262
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.769486203
Short name T595
Test name
Test status
Simulation time 15908961 ps
CPU time 0.63 seconds
Started Jul 07 05:28:28 PM PDT 24
Finished Jul 07 05:28:29 PM PDT 24
Peak memory 195320 kb
Host smart-0aaeebfe-be92-4bfd-931e-3f4cf2881abf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769486203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.769486203
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1361460372
Short name T628
Test name
Test status
Simulation time 15429059 ps
CPU time 0.61 seconds
Started Jul 07 05:28:49 PM PDT 24
Finished Jul 07 05:28:50 PM PDT 24
Peak memory 195184 kb
Host smart-c5bd3a42-dede-4da2-be02-6c3228193d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361460372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1361460372
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2711976966
Short name T574
Test name
Test status
Simulation time 12414734 ps
CPU time 0.57 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 195196 kb
Host smart-ccb7708d-c39d-4718-8219-6e1abb360a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711976966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2711976966
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.4232559574
Short name T646
Test name
Test status
Simulation time 32332952 ps
CPU time 0.63 seconds
Started Jul 07 05:28:45 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 195248 kb
Host smart-9ebd1fec-2545-4650-a781-ca6114b9da58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232559574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.4232559574
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2497729346
Short name T572
Test name
Test status
Simulation time 16140362 ps
CPU time 0.57 seconds
Started Jul 07 05:28:54 PM PDT 24
Finished Jul 07 05:28:55 PM PDT 24
Peak memory 195420 kb
Host smart-df4a2164-9afc-4fac-969f-353c3339568e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497729346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2497729346
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1818154296
Short name T645
Test name
Test status
Simulation time 42173365 ps
CPU time 0.58 seconds
Started Jul 07 05:29:01 PM PDT 24
Finished Jul 07 05:29:02 PM PDT 24
Peak memory 195168 kb
Host smart-2d2b4104-e6cb-48c1-bde9-192ac4a7276a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818154296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1818154296
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.4000031030
Short name T545
Test name
Test status
Simulation time 35292784 ps
CPU time 0.59 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 195220 kb
Host smart-3a56455f-98ad-4b3d-bc32-f275ebce8ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000031030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.4000031030
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1326625367
Short name T104
Test name
Test status
Simulation time 1237903187 ps
CPU time 5.78 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:30 PM PDT 24
Peak memory 200084 kb
Host smart-78e0e5b7-7aae-4ac9-9915-15794bcb349c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326625367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1326625367
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3314493999
Short name T601
Test name
Test status
Simulation time 3747836103 ps
CPU time 15.32 seconds
Started Jul 07 05:28:31 PM PDT 24
Finished Jul 07 05:28:47 PM PDT 24
Peak memory 200416 kb
Host smart-f0f7d351-76ca-4e76-aa97-a528dacb41e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314493999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3314493999
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4190570533
Short name T593
Test name
Test status
Simulation time 291440535 ps
CPU time 0.83 seconds
Started Jul 07 05:28:23 PM PDT 24
Finished Jul 07 05:28:25 PM PDT 24
Peak memory 199168 kb
Host smart-602fae22-d6c2-45de-a876-4f0b14349c89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190570533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.4190570533
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.601112807
Short name T527
Test name
Test status
Simulation time 29630431 ps
CPU time 1.35 seconds
Started Jul 07 05:28:33 PM PDT 24
Finished Jul 07 05:28:35 PM PDT 24
Peak memory 200336 kb
Host smart-2f7546a0-38af-4865-9d44-8b15a7482481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601112807 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.601112807
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1360787846
Short name T103
Test name
Test status
Simulation time 17301862 ps
CPU time 0.98 seconds
Started Jul 07 05:28:29 PM PDT 24
Finished Jul 07 05:28:31 PM PDT 24
Peak memory 200152 kb
Host smart-aa6c53bb-09fe-401d-9d1d-a9b6f191a807
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360787846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1360787846
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3556481547
Short name T532
Test name
Test status
Simulation time 41987685 ps
CPU time 0.58 seconds
Started Jul 07 05:28:16 PM PDT 24
Finished Jul 07 05:28:17 PM PDT 24
Peak memory 195204 kb
Host smart-e298ecef-5044-431c-8a38-9d06d8f6dfab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556481547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3556481547
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1017979193
Short name T116
Test name
Test status
Simulation time 121074253 ps
CPU time 1.64 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:34 PM PDT 24
Peak memory 200280 kb
Host smart-36a77bd1-4acc-481f-a1b7-db3e42aeb31b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017979193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1017979193
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.639627341
Short name T568
Test name
Test status
Simulation time 57255758 ps
CPU time 2.88 seconds
Started Jul 07 05:28:31 PM PDT 24
Finished Jul 07 05:28:34 PM PDT 24
Peak memory 200284 kb
Host smart-f18471b8-78b2-4c2e-a01b-b70cde549de3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639627341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.639627341
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2957441848
Short name T75
Test name
Test status
Simulation time 981420442 ps
CPU time 2.86 seconds
Started Jul 07 05:28:22 PM PDT 24
Finished Jul 07 05:28:25 PM PDT 24
Peak memory 200276 kb
Host smart-e4d35cf4-2281-4fbb-9a13-c89c4d2c49f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957441848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2957441848
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2097830687
Short name T529
Test name
Test status
Simulation time 14880183 ps
CPU time 0.59 seconds
Started Jul 07 05:28:28 PM PDT 24
Finished Jul 07 05:28:34 PM PDT 24
Peak memory 195192 kb
Host smart-c20218bb-4fd8-464c-a8a2-2d377f62891d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097830687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2097830687
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.726366890
Short name T607
Test name
Test status
Simulation time 13801161 ps
CPU time 0.59 seconds
Started Jul 07 05:28:45 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 195188 kb
Host smart-ffb05957-0fa7-4eef-940a-74f2e876e90f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726366890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.726366890
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3730125523
Short name T650
Test name
Test status
Simulation time 27810748 ps
CPU time 0.6 seconds
Started Jul 07 05:28:53 PM PDT 24
Finished Jul 07 05:28:54 PM PDT 24
Peak memory 195560 kb
Host smart-c7391e2a-133e-4e7b-9d27-11578edf8db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730125523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3730125523
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.4283864570
Short name T610
Test name
Test status
Simulation time 50708051 ps
CPU time 0.58 seconds
Started Jul 07 05:28:47 PM PDT 24
Finished Jul 07 05:28:48 PM PDT 24
Peak memory 195292 kb
Host smart-7e964c1c-1a87-4935-b55f-ec50d0f83561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283864570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.4283864570
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3374680383
Short name T531
Test name
Test status
Simulation time 14140746 ps
CPU time 0.61 seconds
Started Jul 07 05:28:48 PM PDT 24
Finished Jul 07 05:28:49 PM PDT 24
Peak memory 195592 kb
Host smart-e7f2dec4-1f0d-4e6d-bf02-751033798a5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374680383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3374680383
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2033813439
Short name T643
Test name
Test status
Simulation time 31586029 ps
CPU time 0.66 seconds
Started Jul 07 05:28:43 PM PDT 24
Finished Jul 07 05:28:44 PM PDT 24
Peak memory 195220 kb
Host smart-8c995920-3a43-4b57-9bbb-693953c0ca06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033813439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2033813439
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3907523554
Short name T573
Test name
Test status
Simulation time 41715961 ps
CPU time 0.58 seconds
Started Jul 07 05:28:52 PM PDT 24
Finished Jul 07 05:28:53 PM PDT 24
Peak memory 195160 kb
Host smart-2398ec20-06fc-4791-a2dd-defa3d068207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907523554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3907523554
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3075370556
Short name T575
Test name
Test status
Simulation time 14898488 ps
CPU time 0.59 seconds
Started Jul 07 05:28:40 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 195260 kb
Host smart-8efa51c6-894f-47fb-8c2a-f8a62a9877fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075370556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3075370556
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1694737300
Short name T592
Test name
Test status
Simulation time 34414058 ps
CPU time 0.58 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 195136 kb
Host smart-d5e3085c-f21b-4819-926b-c4bef5537c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694737300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1694737300
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.849085104
Short name T586
Test name
Test status
Simulation time 63135927 ps
CPU time 0.58 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 195140 kb
Host smart-ce003233-fa57-4905-b15e-e0c41211bfd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849085104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.849085104
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3721224055
Short name T560
Test name
Test status
Simulation time 96528682 ps
CPU time 3.04 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:36 PM PDT 24
Peak memory 215700 kb
Host smart-840f66bc-df85-4a81-88a6-0bc2ee12d2fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721224055 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3721224055
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3696549436
Short name T112
Test name
Test status
Simulation time 109874097 ps
CPU time 0.82 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:34 PM PDT 24
Peak memory 199624 kb
Host smart-21a87978-4a96-42c8-8f08-50c762c2e4b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696549436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3696549436
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2073049260
Short name T588
Test name
Test status
Simulation time 22098790 ps
CPU time 0.59 seconds
Started Jul 07 05:28:30 PM PDT 24
Finished Jul 07 05:28:32 PM PDT 24
Peak memory 195160 kb
Host smart-e993166e-ba24-4116-b0f1-e20b553560a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073049260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2073049260
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2399008661
Short name T120
Test name
Test status
Simulation time 127095042 ps
CPU time 1.84 seconds
Started Jul 07 05:28:21 PM PDT 24
Finished Jul 07 05:28:24 PM PDT 24
Peak memory 200356 kb
Host smart-ef2cbf81-5afb-4167-8591-688146949781
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399008661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2399008661
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2195616365
Short name T557
Test name
Test status
Simulation time 147825627 ps
CPU time 3.88 seconds
Started Jul 07 05:28:15 PM PDT 24
Finished Jul 07 05:28:19 PM PDT 24
Peak memory 200344 kb
Host smart-3c955126-e44a-4a6a-ba28-34ff6d8b3bff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195616365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2195616365
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1626910703
Short name T615
Test name
Test status
Simulation time 746617245 ps
CPU time 3.18 seconds
Started Jul 07 05:28:18 PM PDT 24
Finished Jul 07 05:28:21 PM PDT 24
Peak memory 200208 kb
Host smart-6e70d946-4ce3-41b7-8574-fe8d7d45b2da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626910703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1626910703
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1386631039
Short name T584
Test name
Test status
Simulation time 281503215 ps
CPU time 1.72 seconds
Started Jul 07 05:28:21 PM PDT 24
Finished Jul 07 05:28:23 PM PDT 24
Peak memory 200344 kb
Host smart-c076a3c3-0673-4520-9605-59c67c433ec5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386631039 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1386631039
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.925038095
Short name T578
Test name
Test status
Simulation time 62082784 ps
CPU time 0.72 seconds
Started Jul 07 05:28:27 PM PDT 24
Finished Jul 07 05:28:29 PM PDT 24
Peak memory 198572 kb
Host smart-6e3738e9-c463-4892-993f-1d0418c4483e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925038095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.925038095
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2880373642
Short name T561
Test name
Test status
Simulation time 25651790 ps
CPU time 0.62 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:33 PM PDT 24
Peak memory 195312 kb
Host smart-ee3de7c6-1116-46a8-9822-61d3fc5f2159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880373642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2880373642
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4147275703
Short name T630
Test name
Test status
Simulation time 64471401 ps
CPU time 1.26 seconds
Started Jul 07 05:28:29 PM PDT 24
Finished Jul 07 05:28:31 PM PDT 24
Peak memory 200184 kb
Host smart-3aa3b97a-6308-40a0-baa7-a5d67b247aa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147275703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.4147275703
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3884815972
Short name T590
Test name
Test status
Simulation time 696354511 ps
CPU time 2.85 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:34 PM PDT 24
Peak memory 200292 kb
Host smart-7874edc8-6dcd-4940-b76c-4c7f42121abd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884815972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3884815972
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3605120003
Short name T634
Test name
Test status
Simulation time 481704947 ps
CPU time 4.32 seconds
Started Jul 07 05:28:18 PM PDT 24
Finished Jul 07 05:28:23 PM PDT 24
Peak memory 200264 kb
Host smart-c206ccd8-20ef-4b08-b67e-8b8249a182c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605120003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3605120003
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2780755170
Short name T550
Test name
Test status
Simulation time 44615783 ps
CPU time 1.35 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 200360 kb
Host smart-e426efeb-d3f6-4ce4-9cbd-3232405499bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780755170 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2780755170
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2794032088
Short name T609
Test name
Test status
Simulation time 35645868 ps
CPU time 0.67 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 198176 kb
Host smart-424dc59e-49cd-40de-87d4-4357838ae13c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794032088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2794032088
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.951791558
Short name T556
Test name
Test status
Simulation time 43861914 ps
CPU time 0.58 seconds
Started Jul 07 05:28:33 PM PDT 24
Finished Jul 07 05:28:34 PM PDT 24
Peak memory 195188 kb
Host smart-0f3bfc18-4bf0-4f7a-abed-febcc4a6aa01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951791558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.951791558
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1873407032
Short name T589
Test name
Test status
Simulation time 157059556 ps
CPU time 1.94 seconds
Started Jul 07 05:28:43 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 200236 kb
Host smart-40bd97c9-5590-4631-a069-93fbbe6217c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873407032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1873407032
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.6149976
Short name T585
Test name
Test status
Simulation time 142098671 ps
CPU time 2.94 seconds
Started Jul 07 05:28:28 PM PDT 24
Finished Jul 07 05:28:32 PM PDT 24
Peak memory 200316 kb
Host smart-dbe75186-4a7c-4e23-a708-43de549da29c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6149976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.6149976
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.584586357
Short name T583
Test name
Test status
Simulation time 338662266 ps
CPU time 1.93 seconds
Started Jul 07 05:28:54 PM PDT 24
Finished Jul 07 05:28:56 PM PDT 24
Peak memory 200240 kb
Host smart-48020d13-bf32-4b01-9f38-03948b4c8cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584586357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.584586357
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2315851194
Short name T533
Test name
Test status
Simulation time 275879101 ps
CPU time 2.18 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:28:53 PM PDT 24
Peak memory 200288 kb
Host smart-e436593a-9c16-4dca-a2a2-87ffcc7b9c7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315851194 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2315851194
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2958261877
Short name T109
Test name
Test status
Simulation time 35324169 ps
CPU time 0.89 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 200124 kb
Host smart-e922e0da-1b4e-40ff-bce6-0e524040a3f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958261877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2958261877
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.907596539
Short name T543
Test name
Test status
Simulation time 10713601 ps
CPU time 0.58 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:36 PM PDT 24
Peak memory 195268 kb
Host smart-ec5d03d7-c540-4b30-83ef-779dae632c7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907596539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.907596539
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1727901138
Short name T114
Test name
Test status
Simulation time 77288171 ps
CPU time 1.64 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:37 PM PDT 24
Peak memory 200264 kb
Host smart-428cfaf7-feaf-42e0-af8f-f982dbc2ab7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727901138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1727901138
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1133681574
Short name T571
Test name
Test status
Simulation time 136158667 ps
CPU time 3.28 seconds
Started Jul 07 05:28:34 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 200348 kb
Host smart-ec876574-0d53-4563-bc75-37cdf6fe01b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133681574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1133681574
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4282329166
Short name T554
Test name
Test status
Simulation time 372044199 ps
CPU time 1.79 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 200332 kb
Host smart-ebc00e1e-e2fa-4307-9aa8-1209e65320f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282329166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4282329166
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4176875929
Short name T644
Test name
Test status
Simulation time 59913832 ps
CPU time 2.07 seconds
Started Jul 07 05:28:51 PM PDT 24
Finished Jul 07 05:28:53 PM PDT 24
Peak memory 200244 kb
Host smart-48e903bb-237d-4dbc-aa2b-9bf066c89c4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176875929 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.4176875929
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.37683997
Short name T618
Test name
Test status
Simulation time 48212923 ps
CPU time 0.68 seconds
Started Jul 07 05:28:34 PM PDT 24
Finished Jul 07 05:28:36 PM PDT 24
Peak memory 198432 kb
Host smart-072c18f8-c9b1-41af-a087-6861ee568026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37683997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.37683997
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.4179378898
Short name T632
Test name
Test status
Simulation time 16566832 ps
CPU time 0.6 seconds
Started Jul 07 05:28:25 PM PDT 24
Finished Jul 07 05:28:26 PM PDT 24
Peak memory 195272 kb
Host smart-57194c79-6e2c-438c-a9ce-fa0eb2433a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179378898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4179378898
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3770147673
Short name T559
Test name
Test status
Simulation time 113688403 ps
CPU time 2.28 seconds
Started Jul 07 05:28:34 PM PDT 24
Finished Jul 07 05:28:37 PM PDT 24
Peak memory 200136 kb
Host smart-3661fecf-b85b-4cb2-a8aa-968384556492
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770147673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3770147673
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3586293612
Short name T651
Test name
Test status
Simulation time 68331868 ps
CPU time 3.3 seconds
Started Jul 07 05:28:34 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 200340 kb
Host smart-9f9a63e1-8e6c-4314-9dcc-9d68dd69ff32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586293612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3586293612
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2292966957
Short name T653
Test name
Test status
Simulation time 459909151 ps
CPU time 1.89 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:28:53 PM PDT 24
Peak memory 200248 kb
Host smart-292a2af6-9998-47ea-9e34-2c474af97b92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292966957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2292966957
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2488028452
Short name T257
Test name
Test status
Simulation time 19330832 ps
CPU time 0.59 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:30:51 PM PDT 24
Peak memory 196120 kb
Host smart-3ffb6a94-94f4-48c3-ac74-71ee3c09749d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488028452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2488028452
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2611978486
Short name T70
Test name
Test status
Simulation time 32304165 ps
CPU time 1.89 seconds
Started Jul 07 05:30:48 PM PDT 24
Finished Jul 07 05:30:51 PM PDT 24
Peak memory 200352 kb
Host smart-de9ff5fa-5e01-49a0-924e-8ce583766c50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611978486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2611978486
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1155433754
Short name T441
Test name
Test status
Simulation time 9367725847 ps
CPU time 60.92 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:31:44 PM PDT 24
Peak memory 208572 kb
Host smart-2bfad89b-eae2-4979-9e52-c363f434ae26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155433754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1155433754
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2587468258
Short name T240
Test name
Test status
Simulation time 25596829860 ps
CPU time 1048.11 seconds
Started Jul 07 05:30:45 PM PDT 24
Finished Jul 07 05:48:13 PM PDT 24
Peak memory 712496 kb
Host smart-bc973ff9-cdd4-4a79-aaf2-bd143695977a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587468258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2587468258
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.681603819
Short name T290
Test name
Test status
Simulation time 244299316369 ps
CPU time 227.63 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:34:36 PM PDT 24
Peak memory 200316 kb
Host smart-c0b98369-1dd6-456d-b064-84df363af1f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681603819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.681603819
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.729763709
Short name T252
Test name
Test status
Simulation time 67146479 ps
CPU time 3.66 seconds
Started Jul 07 05:30:50 PM PDT 24
Finished Jul 07 05:30:54 PM PDT 24
Peak memory 200316 kb
Host smart-d1f344e8-7d72-48c8-98c6-0172ef502240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729763709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.729763709
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1644611774
Short name T66
Test name
Test status
Simulation time 185218956 ps
CPU time 0.8 seconds
Started Jul 07 05:30:51 PM PDT 24
Finished Jul 07 05:30:53 PM PDT 24
Peak memory 218204 kb
Host smart-beb76a5c-a215-49da-adec-b2213a34b28c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644611774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1644611774
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1508220058
Short name T384
Test name
Test status
Simulation time 1276393187 ps
CPU time 3.59 seconds
Started Jul 07 05:30:54 PM PDT 24
Finished Jul 07 05:30:58 PM PDT 24
Peak memory 200340 kb
Host smart-e5ede166-5c11-46ad-9ae7-937e16c21209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508220058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1508220058
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2992706558
Short name T438
Test name
Test status
Simulation time 92323531381 ps
CPU time 733.51 seconds
Started Jul 07 05:30:42 PM PDT 24
Finished Jul 07 05:42:57 PM PDT 24
Peak memory 557812 kb
Host smart-c536b003-c83c-46ea-aa43-080980813dd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992706558 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2992706558
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2788391011
Short name T24
Test name
Test status
Simulation time 417243187127 ps
CPU time 657.07 seconds
Started Jul 07 05:30:52 PM PDT 24
Finished Jul 07 05:41:49 PM PDT 24
Peak memory 666112 kb
Host smart-2cd65d41-d841-4aa8-a49d-7262f607f413
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788391011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2788391011
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.4292952062
Short name T454
Test name
Test status
Simulation time 6667173573 ps
CPU time 62.73 seconds
Started Jul 07 05:30:48 PM PDT 24
Finished Jul 07 05:31:52 PM PDT 24
Peak memory 200380 kb
Host smart-33da1e78-92f9-4866-b62f-9316f390a7b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4292952062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.4292952062
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2378834349
Short name T326
Test name
Test status
Simulation time 3535916133 ps
CPU time 65.73 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:31:54 PM PDT 24
Peak memory 200328 kb
Host smart-34df90af-48d0-423f-ac31-8e4798d7b640
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2378834349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2378834349
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3785274283
Short name T46
Test name
Test status
Simulation time 11587391582 ps
CPU time 87 seconds
Started Jul 07 05:30:48 PM PDT 24
Finished Jul 07 05:32:16 PM PDT 24
Peak memory 200324 kb
Host smart-a475d09f-6911-48ed-a6d2-1814dbfc00fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3785274283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3785274283
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.4217270008
Short name T48
Test name
Test status
Simulation time 92439420153 ps
CPU time 633.09 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:41:21 PM PDT 24
Peak memory 200340 kb
Host smart-16ea8df0-bc6e-4a95-8342-cae0c7686e51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4217270008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.4217270008
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.54348051
Short name T135
Test name
Test status
Simulation time 92841622562 ps
CPU time 2226.44 seconds
Started Jul 07 05:30:44 PM PDT 24
Finished Jul 07 06:07:51 PM PDT 24
Peak memory 216092 kb
Host smart-1a27c3f4-d483-4842-944a-99c0728b5b47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=54348051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.54348051
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.195830593
Short name T437
Test name
Test status
Simulation time 32473654120 ps
CPU time 113.75 seconds
Started Jul 07 05:30:44 PM PDT 24
Finished Jul 07 05:32:39 PM PDT 24
Peak memory 200356 kb
Host smart-bde397e1-5081-46d6-9329-282597b7ad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195830593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.195830593
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3621955631
Short name T254
Test name
Test status
Simulation time 13022212 ps
CPU time 0.62 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:31:03 PM PDT 24
Peak memory 195820 kb
Host smart-c6559837-d432-4cad-8e6e-4327a857a389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621955631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3621955631
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3088207943
Short name T464
Test name
Test status
Simulation time 1820914875 ps
CPU time 103.16 seconds
Started Jul 07 05:30:50 PM PDT 24
Finished Jul 07 05:32:34 PM PDT 24
Peak memory 200268 kb
Host smart-889a0616-dec4-4e18-975b-1335e84eaa5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088207943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3088207943
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.830441718
Short name T229
Test name
Test status
Simulation time 6228027820 ps
CPU time 1236.32 seconds
Started Jul 07 05:31:05 PM PDT 24
Finished Jul 07 05:51:43 PM PDT 24
Peak memory 751728 kb
Host smart-32c9678a-7a99-41f1-abe9-1b3b3ad271f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830441718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.830441718
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1296054814
Short name T220
Test name
Test status
Simulation time 29432705486 ps
CPU time 180.03 seconds
Started Jul 07 05:30:44 PM PDT 24
Finished Jul 07 05:33:45 PM PDT 24
Peak memory 200320 kb
Host smart-3050fc22-fe05-4ac5-ae61-0b4e275e1d37
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296054814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1296054814
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.216778028
Short name T470
Test name
Test status
Simulation time 11017270109 ps
CPU time 179.89 seconds
Started Jul 07 05:30:53 PM PDT 24
Finished Jul 07 05:33:53 PM PDT 24
Peak memory 216684 kb
Host smart-db3944e1-a038-48eb-94a2-8ac053190831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216778028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.216778028
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.3308744417
Short name T21
Test name
Test status
Simulation time 1557992383 ps
CPU time 13.3 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:31:09 PM PDT 24
Peak memory 200308 kb
Host smart-10a7c01c-f7eb-4335-831c-10b37c68f074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308744417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3308744417
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1945693503
Short name T82
Test name
Test status
Simulation time 83219795047 ps
CPU time 776.65 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:44:00 PM PDT 24
Peak memory 626232 kb
Host smart-51263d31-9a2b-4b2b-81dd-d0e510b69956
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945693503 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1945693503
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3720328289
Short name T19
Test name
Test status
Simulation time 90148553594 ps
CPU time 1561.49 seconds
Started Jul 07 05:30:56 PM PDT 24
Finished Jul 07 05:56:58 PM PDT 24
Peak memory 462724 kb
Host smart-288381f6-1796-4d4a-8c8e-bd29c3939dce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720328289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3720328289
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1505572798
Short name T276
Test name
Test status
Simulation time 23921835089 ps
CPU time 74.01 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:32:01 PM PDT 24
Peak memory 200368 kb
Host smart-8aec6ae4-4118-49d1-9b2c-225d112269c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1505572798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1505572798
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1049111557
Short name T167
Test name
Test status
Simulation time 6931769632 ps
CPU time 73.79 seconds
Started Jul 07 05:30:54 PM PDT 24
Finished Jul 07 05:32:08 PM PDT 24
Peak memory 200356 kb
Host smart-ada7f952-8198-4560-8950-63fe0f55e0f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1049111557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1049111557
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1755302912
Short name T362
Test name
Test status
Simulation time 12713882870 ps
CPU time 129.79 seconds
Started Jul 07 05:30:58 PM PDT 24
Finished Jul 07 05:33:08 PM PDT 24
Peak memory 200412 kb
Host smart-b6357f6b-42a7-41fc-b0e0-b475b0ba02f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1755302912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1755302912
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3410042354
Short name T226
Test name
Test status
Simulation time 179529995222 ps
CPU time 712.47 seconds
Started Jul 07 05:30:46 PM PDT 24
Finished Jul 07 05:42:40 PM PDT 24
Peak memory 200320 kb
Host smart-c00da454-ff86-433b-85c2-ed819be1d38c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3410042354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3410042354
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.566687286
Short name T339
Test name
Test status
Simulation time 138025961174 ps
CPU time 2539.72 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 06:13:23 PM PDT 24
Peak memory 215776 kb
Host smart-17b6d49b-34db-4d01-a515-aaedfec56fee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=566687286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.566687286
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2564313546
Short name T374
Test name
Test status
Simulation time 821127151453 ps
CPU time 2583.99 seconds
Started Jul 07 05:31:09 PM PDT 24
Finished Jul 07 06:14:14 PM PDT 24
Peak memory 216580 kb
Host smart-3d5580d6-ab57-4655-bcea-61265cfe81be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2564313546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2564313546
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2483572360
Short name T367
Test name
Test status
Simulation time 33970577468 ps
CPU time 105.01 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:32:53 PM PDT 24
Peak memory 200424 kb
Host smart-09525fd5-e4e8-43b5-8a06-17e9f7f54034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483572360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2483572360
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2765210981
Short name T196
Test name
Test status
Simulation time 139755611 ps
CPU time 0.59 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:31:08 PM PDT 24
Peak memory 195196 kb
Host smart-5535bb79-bcb8-44bf-981c-7d911222767d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765210981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2765210981
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4290691504
Short name T253
Test name
Test status
Simulation time 17423594163 ps
CPU time 90.84 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:32:26 PM PDT 24
Peak memory 208552 kb
Host smart-2f5bd391-7140-4560-9a9f-1e22fd20ab0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290691504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4290691504
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1725266654
Short name T158
Test name
Test status
Simulation time 2730922715 ps
CPU time 39.95 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:41 PM PDT 24
Peak memory 200288 kb
Host smart-5c557100-c104-4dba-819f-07092f82b0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725266654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1725266654
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1835157225
Short name T353
Test name
Test status
Simulation time 2680320977 ps
CPU time 474.57 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:39:06 PM PDT 24
Peak memory 691924 kb
Host smart-1b7e0860-a234-45dc-874b-254fd75975ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835157225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1835157225
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1786496373
Short name T311
Test name
Test status
Simulation time 3656276612 ps
CPU time 11.34 seconds
Started Jul 07 05:30:59 PM PDT 24
Finished Jul 07 05:31:10 PM PDT 24
Peak memory 200336 kb
Host smart-ac4abe5f-8f4e-4d24-af90-e9d75e458651
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786496373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1786496373
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3086074040
Short name T39
Test name
Test status
Simulation time 9990343237 ps
CPU time 185.58 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:34:09 PM PDT 24
Peak memory 208600 kb
Host smart-6e8fd85d-7309-4e42-a332-6ba331695d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086074040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3086074040
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3875473223
Short name T489
Test name
Test status
Simulation time 613591077 ps
CPU time 7.12 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:31:03 PM PDT 24
Peak memory 200308 kb
Host smart-fab0973a-abb3-4df1-8527-bb7013ba5c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875473223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3875473223
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.4128993332
Short name T27
Test name
Test status
Simulation time 50665739196 ps
CPU time 1161.65 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:50:27 PM PDT 24
Peak memory 658964 kb
Host smart-bb5ea3de-28bf-4431-9a22-f79f987ad092
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128993332 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.4128993332
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1644266063
Short name T248
Test name
Test status
Simulation time 8304530386 ps
CPU time 30.26 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:31:39 PM PDT 24
Peak memory 200408 kb
Host smart-debf2c4f-5781-44d7-8313-568d13f36779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644266063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1644266063
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1895409010
Short name T313
Test name
Test status
Simulation time 2780952398 ps
CPU time 45.51 seconds
Started Jul 07 05:30:58 PM PDT 24
Finished Jul 07 05:31:44 PM PDT 24
Peak memory 200360 kb
Host smart-9b759d5a-1910-414a-b1a1-ca0ceddee5ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1895409010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1895409010
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3365421467
Short name T197
Test name
Test status
Simulation time 3565614554 ps
CPU time 46.45 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:31:51 PM PDT 24
Peak memory 200360 kb
Host smart-af8bd882-73df-4a52-beef-a3cf2bb4a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365421467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3365421467
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.915005015
Short name T403
Test name
Test status
Simulation time 8656927229 ps
CPU time 290.35 seconds
Started Jul 07 05:31:00 PM PDT 24
Finished Jul 07 05:35:51 PM PDT 24
Peak memory 667592 kb
Host smart-027c1c62-bb6d-4485-80e6-244bf21dc477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=915005015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.915005015
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2117996630
Short name T407
Test name
Test status
Simulation time 41402193143 ps
CPU time 123.16 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:33:10 PM PDT 24
Peak memory 200388 kb
Host smart-73e509f2-ea2f-4860-bcb0-7c7975de2afb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117996630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2117996630
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3184559533
Short name T154
Test name
Test status
Simulation time 128521259162 ps
CPU time 130.06 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:33:06 PM PDT 24
Peak memory 200404 kb
Host smart-ad6b3ac3-8307-4fef-a2ab-e2b224663643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184559533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3184559533
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3374345202
Short name T216
Test name
Test status
Simulation time 533232230 ps
CPU time 8.65 seconds
Started Jul 07 05:31:09 PM PDT 24
Finished Jul 07 05:31:18 PM PDT 24
Peak memory 200344 kb
Host smart-f47c2d89-bf13-4abb-a2b3-befbb8c9995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374345202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3374345202
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1353968394
Short name T210
Test name
Test status
Simulation time 283966098249 ps
CPU time 2173.73 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 06:07:16 PM PDT 24
Peak memory 739040 kb
Host smart-ccd70808-d650-4b6e-9af3-7db2315291bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353968394 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1353968394
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3920985994
Short name T315
Test name
Test status
Simulation time 17185257372 ps
CPU time 81.97 seconds
Started Jul 07 05:31:00 PM PDT 24
Finished Jul 07 05:32:23 PM PDT 24
Peak memory 200392 kb
Host smart-39fb2a2b-02a7-40ba-9ed1-97ea7829c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920985994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3920985994
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1058054208
Short name T209
Test name
Test status
Simulation time 40146364 ps
CPU time 0.58 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:31:03 PM PDT 24
Peak memory 195152 kb
Host smart-0c31f8c1-e9ca-45af-b713-8368d04fc193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058054208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1058054208
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.193793135
Short name T524
Test name
Test status
Simulation time 373327588 ps
CPU time 10.63 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:12 PM PDT 24
Peak memory 200276 kb
Host smart-5325c4bc-8b5a-4e75-a114-601cec3fc4c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193793135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.193793135
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.483960401
Short name T460
Test name
Test status
Simulation time 143308636 ps
CPU time 7.4 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:09 PM PDT 24
Peak memory 200340 kb
Host smart-5b3024e3-519d-4096-89b3-b1d35d094b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483960401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.483960401
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2490979505
Short name T427
Test name
Test status
Simulation time 14470377553 ps
CPU time 960.01 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:47:02 PM PDT 24
Peak memory 717512 kb
Host smart-4496917f-66ee-47ca-8c2c-019674312941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490979505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2490979505
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2968931735
Short name T469
Test name
Test status
Simulation time 1143316743 ps
CPU time 60.71 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:32:03 PM PDT 24
Peak memory 200232 kb
Host smart-10348db8-266d-44dc-bb08-9b7c9e516dca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968931735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2968931735
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3197589873
Short name T509
Test name
Test status
Simulation time 69703573442 ps
CPU time 129.93 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:33:13 PM PDT 24
Peak memory 200352 kb
Host smart-e4563b67-2f61-46ab-bf61-71ff199547e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197589873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3197589873
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3993155455
Short name T363
Test name
Test status
Simulation time 209237338 ps
CPU time 10.15 seconds
Started Jul 07 05:31:00 PM PDT 24
Finished Jul 07 05:31:11 PM PDT 24
Peak memory 200272 kb
Host smart-7822750d-f48b-4b8c-a9f0-343c66df4dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993155455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3993155455
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2089567575
Short name T97
Test name
Test status
Simulation time 340899211046 ps
CPU time 1472.88 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:55:42 PM PDT 24
Peak memory 652344 kb
Host smart-e35d1e74-84fb-4f96-8367-f16fbc1bc43f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089567575 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2089567575
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.264105676
Short name T99
Test name
Test status
Simulation time 16374649844 ps
CPU time 61.39 seconds
Started Jul 07 05:31:00 PM PDT 24
Finished Jul 07 05:32:02 PM PDT 24
Peak memory 200676 kb
Host smart-1fb601f1-a70d-4d25-889a-a8d1e5d1ea5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264105676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.264105676
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3402795828
Short name T71
Test name
Test status
Simulation time 41632426 ps
CPU time 0.58 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:31:07 PM PDT 24
Peak memory 196184 kb
Host smart-0c03a57f-85b7-4d65-b25a-eb9b63495e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402795828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3402795828
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.684603523
Short name T199
Test name
Test status
Simulation time 1340700344 ps
CPU time 19.55 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:31:30 PM PDT 24
Peak memory 200324 kb
Host smart-b5deb5a5-2730-4327-8855-3670caf02545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684603523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.684603523
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2516075349
Short name T504
Test name
Test status
Simulation time 13446971860 ps
CPU time 51.59 seconds
Started Jul 07 05:30:56 PM PDT 24
Finished Jul 07 05:31:48 PM PDT 24
Peak memory 200368 kb
Host smart-8e18ee99-56ec-4a81-a1e6-c7e3dad9a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516075349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2516075349
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1980782549
Short name T317
Test name
Test status
Simulation time 1789796616 ps
CPU time 92.37 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:32:37 PM PDT 24
Peak memory 541508 kb
Host smart-62a98d16-de57-4a2f-8ec8-85cd5b2c44a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980782549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1980782549
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1885022504
Short name T157
Test name
Test status
Simulation time 24398721788 ps
CPU time 68.05 seconds
Started Jul 07 05:30:56 PM PDT 24
Finished Jul 07 05:32:05 PM PDT 24
Peak memory 200412 kb
Host smart-cd0bf005-341f-41e3-8730-e2442925451d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885022504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1885022504
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.552276312
Short name T44
Test name
Test status
Simulation time 6150790377 ps
CPU time 114.74 seconds
Started Jul 07 05:31:00 PM PDT 24
Finished Jul 07 05:32:55 PM PDT 24
Peak memory 200296 kb
Host smart-4fe6c9c7-2766-4c83-a4a3-06603f37dcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552276312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.552276312
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3152196536
Short name T397
Test name
Test status
Simulation time 1037044982 ps
CPU time 11.93 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:13 PM PDT 24
Peak memory 200272 kb
Host smart-e5279947-2a7e-467f-8b67-ce9f48bba350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152196536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3152196536
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2365004208
Short name T32
Test name
Test status
Simulation time 20396116182 ps
CPU time 560.26 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:40:27 PM PDT 24
Peak memory 200392 kb
Host smart-7201aab2-8d99-48f7-b24d-b845fd69725e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365004208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2365004208
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1559550389
Short name T390
Test name
Test status
Simulation time 18098964307 ps
CPU time 97.58 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:32:41 PM PDT 24
Peak memory 200640 kb
Host smart-871657a1-6f22-4642-9da4-b1b373973291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559550389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1559550389
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.125113462
Short name T387
Test name
Test status
Simulation time 33866820 ps
CPU time 0.58 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:31:04 PM PDT 24
Peak memory 196212 kb
Host smart-4b59574b-e984-4bf6-8e65-a34dc26824f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125113462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.125113462
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2313545105
Short name T163
Test name
Test status
Simulation time 183804039 ps
CPU time 5.93 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:31:11 PM PDT 24
Peak memory 200280 kb
Host smart-30d5e413-5e76-4ab9-b5f6-b57cdfe9edab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313545105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2313545105
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2636307892
Short name T501
Test name
Test status
Simulation time 1399839606 ps
CPU time 73.27 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:32:18 PM PDT 24
Peak memory 200324 kb
Host smart-336b089d-a9cc-4606-b77b-5a76f1224cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636307892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2636307892
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4057579638
Short name T289
Test name
Test status
Simulation time 8502616042 ps
CPU time 775.63 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:44:01 PM PDT 24
Peak memory 715020 kb
Host smart-02f125e5-48de-4fb5-8ad9-e9e0c2b4a276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4057579638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4057579638
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3591707005
Short name T448
Test name
Test status
Simulation time 17867943138 ps
CPU time 19.03 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:21 PM PDT 24
Peak memory 200256 kb
Host smart-1967b64a-3936-4176-ba46-a44f147e58d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591707005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3591707005
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.257742068
Short name T478
Test name
Test status
Simulation time 1987732918 ps
CPU time 109.06 seconds
Started Jul 07 05:30:59 PM PDT 24
Finished Jul 07 05:32:49 PM PDT 24
Peak memory 200320 kb
Host smart-5e097ffc-e15a-4798-a49e-160dbc2b2883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257742068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.257742068
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1567577385
Short name T191
Test name
Test status
Simulation time 65007205 ps
CPU time 1.31 seconds
Started Jul 07 05:30:58 PM PDT 24
Finished Jul 07 05:31:00 PM PDT 24
Peak memory 200236 kb
Host smart-cc92aa2c-7a2f-4fa0-85dd-cce0b28dee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567577385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1567577385
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.510788694
Short name T417
Test name
Test status
Simulation time 26074364829 ps
CPU time 701.96 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:42:44 PM PDT 24
Peak memory 200264 kb
Host smart-77e33286-a825-41f7-be2a-5acc3b6db694
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510788694 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.510788694
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.354307679
Short name T386
Test name
Test status
Simulation time 23034915433 ps
CPU time 108.95 seconds
Started Jul 07 05:30:57 PM PDT 24
Finished Jul 07 05:32:46 PM PDT 24
Peak memory 200396 kb
Host smart-c1afe5d0-0676-4351-878d-1e49c3c7fe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354307679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.354307679
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3077981703
Short name T60
Test name
Test status
Simulation time 40618276 ps
CPU time 0.63 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:31:04 PM PDT 24
Peak memory 196144 kb
Host smart-d98dda9b-42ce-456c-8ebc-f3f9a342b36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077981703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3077981703
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2731321660
Short name T453
Test name
Test status
Simulation time 606662277 ps
CPU time 8.74 seconds
Started Jul 07 05:30:59 PM PDT 24
Finished Jul 07 05:31:08 PM PDT 24
Peak memory 200268 kb
Host smart-8f4edce7-0142-46a9-8bf2-27d750d7fa4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731321660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2731321660
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1387216557
Short name T412
Test name
Test status
Simulation time 10453232775 ps
CPU time 66.72 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:32:15 PM PDT 24
Peak memory 200368 kb
Host smart-164e861b-4860-45c9-9838-79dc09b83f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387216557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1387216557
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1554690637
Short name T198
Test name
Test status
Simulation time 4990430295 ps
CPU time 866.72 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:45:38 PM PDT 24
Peak memory 690628 kb
Host smart-f31e78ea-3787-4d9b-a876-b9e78bdb0283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1554690637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1554690637
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_long_msg.566547104
Short name T156
Test name
Test status
Simulation time 11133679324 ps
CPU time 72.65 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:32:16 PM PDT 24
Peak memory 200436 kb
Host smart-ee0619f8-1352-4010-8023-0034d158afcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566547104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.566547104
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3088231736
Short name T346
Test name
Test status
Simulation time 248506902 ps
CPU time 2.56 seconds
Started Jul 07 05:31:00 PM PDT 24
Finished Jul 07 05:31:03 PM PDT 24
Peak memory 200272 kb
Host smart-cce258b7-950f-45f8-a8bc-5bdcf80469ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088231736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3088231736
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2595645637
Short name T31
Test name
Test status
Simulation time 2048909489 ps
CPU time 53.91 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:31:58 PM PDT 24
Peak memory 200324 kb
Host smart-1c72646d-1541-4b50-9247-6fa2702f8870
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595645637 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2595645637
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.554587069
Short name T352
Test name
Test status
Simulation time 12730624175 ps
CPU time 52.17 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:31:55 PM PDT 24
Peak memory 200396 kb
Host smart-c3a66fc4-f6a0-469d-a574-e4aa537a6739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554587069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.554587069
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.897137288
Short name T168
Test name
Test status
Simulation time 42279533 ps
CPU time 0.62 seconds
Started Jul 07 05:31:09 PM PDT 24
Finished Jul 07 05:31:10 PM PDT 24
Peak memory 196476 kb
Host smart-3ea17bf0-7a1d-4585-9df2-b14f72a58c09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897137288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.897137288
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1622467434
Short name T87
Test name
Test status
Simulation time 2239381636 ps
CPU time 69.21 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:32:11 PM PDT 24
Peak memory 200352 kb
Host smart-f7575d65-a840-4fff-8bdd-427f92c8dcbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622467434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1622467434
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1321285461
Short name T152
Test name
Test status
Simulation time 2522509670 ps
CPU time 47.84 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:49 PM PDT 24
Peak memory 200432 kb
Host smart-ecab5d53-31c5-43dc-9df3-ec80d4bcbe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321285461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1321285461
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1480412955
Short name T88
Test name
Test status
Simulation time 4132532486 ps
CPU time 693.91 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:42:43 PM PDT 24
Peak memory 689192 kb
Host smart-2497b603-7154-4026-a82f-908d39f02901
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480412955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1480412955
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3028706115
Short name T392
Test name
Test status
Simulation time 9335805543 ps
CPU time 150.89 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:33:39 PM PDT 24
Peak memory 200260 kb
Host smart-7af4cbba-82e1-4b79-af9a-8fa54cb031cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028706115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3028706115
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.245970956
Short name T344
Test name
Test status
Simulation time 2128890324 ps
CPU time 95.78 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:32:41 PM PDT 24
Peak memory 200360 kb
Host smart-3edff0b1-5032-456d-b206-2b76e65eab5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245970956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.245970956
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2217108902
Short name T215
Test name
Test status
Simulation time 2463245975 ps
CPU time 8.62 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:31:13 PM PDT 24
Peak memory 200236 kb
Host smart-788c359e-9d18-495e-8158-4682fc84eed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217108902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2217108902
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.590054115
Short name T459
Test name
Test status
Simulation time 23352484166 ps
CPU time 813.21 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:44:36 PM PDT 24
Peak memory 675364 kb
Host smart-082081f9-7e39-4c3c-be4e-7d2ce0b1f0ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590054115 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.590054115
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2041232611
Short name T250
Test name
Test status
Simulation time 1148108728 ps
CPU time 58.04 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:32:09 PM PDT 24
Peak memory 200296 kb
Host smart-f91e2db6-b1c2-4350-9a17-34d7cf0b8430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041232611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2041232611
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1892517370
Short name T400
Test name
Test status
Simulation time 11839664 ps
CPU time 0.6 seconds
Started Jul 07 05:31:05 PM PDT 24
Finished Jul 07 05:31:07 PM PDT 24
Peak memory 195156 kb
Host smart-4a8c323d-6ad8-4c2f-94d8-89bec9181f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892517370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1892517370
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2589801354
Short name T223
Test name
Test status
Simulation time 2459457239 ps
CPU time 33.39 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:35 PM PDT 24
Peak memory 200364 kb
Host smart-4c1b73db-7dab-48aa-80e1-1142f43e9085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2589801354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2589801354
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2993209755
Short name T468
Test name
Test status
Simulation time 1949240694 ps
CPU time 48.09 seconds
Started Jul 07 05:31:07 PM PDT 24
Finished Jul 07 05:31:55 PM PDT 24
Peak memory 200316 kb
Host smart-9d44a2ab-2855-45b6-9e0b-f721006dc466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993209755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2993209755
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.868424019
Short name T79
Test name
Test status
Simulation time 5881215573 ps
CPU time 1103.04 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:49:35 PM PDT 24
Peak memory 741840 kb
Host smart-52ddf55f-5aa3-4654-b4bf-007b925abd25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868424019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.868424019
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1705442983
Short name T182
Test name
Test status
Simulation time 13958909081 ps
CPU time 145.54 seconds
Started Jul 07 05:31:00 PM PDT 24
Finished Jul 07 05:33:26 PM PDT 24
Peak memory 200336 kb
Host smart-2c995946-102c-4e89-850c-6607d78c4239
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705442983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1705442983
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3944075885
Short name T143
Test name
Test status
Simulation time 8302765664 ps
CPU time 151.32 seconds
Started Jul 07 05:31:05 PM PDT 24
Finished Jul 07 05:33:37 PM PDT 24
Peak memory 200696 kb
Host smart-80788c3b-9728-4971-b2b0-6eab0a8fd1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944075885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3944075885
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1665193473
Short name T416
Test name
Test status
Simulation time 408521551 ps
CPU time 5.05 seconds
Started Jul 07 05:31:05 PM PDT 24
Finished Jul 07 05:31:11 PM PDT 24
Peak memory 200252 kb
Host smart-a411c1a1-a8e2-4dcb-8b26-5cbbf069689e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665193473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1665193473
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1190298193
Short name T213
Test name
Test status
Simulation time 25735142069 ps
CPU time 334.47 seconds
Started Jul 07 05:31:07 PM PDT 24
Finished Jul 07 05:36:42 PM PDT 24
Peak memory 200832 kb
Host smart-170e6fd8-8250-46d9-963c-82351b2167a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190298193 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1190298193
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2339098772
Short name T516
Test name
Test status
Simulation time 957562424 ps
CPU time 49.85 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:31:57 PM PDT 24
Peak memory 200240 kb
Host smart-5db9392f-1e97-46cf-a5a1-4fa9ab0a5cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339098772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2339098772
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3554193312
Short name T514
Test name
Test status
Simulation time 47474152 ps
CPU time 0.58 seconds
Started Jul 07 05:31:07 PM PDT 24
Finished Jul 07 05:31:08 PM PDT 24
Peak memory 196720 kb
Host smart-a1d80247-c12a-4df3-b37a-42ab467ac0cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554193312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3554193312
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3582617222
Short name T38
Test name
Test status
Simulation time 397685384 ps
CPU time 2.03 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:31:07 PM PDT 24
Peak memory 200228 kb
Host smart-5980a51f-3113-457a-8261-b6dd9195677d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3582617222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3582617222
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2369156480
Short name T270
Test name
Test status
Simulation time 206597439 ps
CPU time 2.99 seconds
Started Jul 07 05:31:07 PM PDT 24
Finished Jul 07 05:31:10 PM PDT 24
Peak memory 200304 kb
Host smart-dffed701-ee2f-4c09-95fc-b9326f1a2b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369156480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2369156480
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2734176583
Short name T69
Test name
Test status
Simulation time 42403971428 ps
CPU time 1079.19 seconds
Started Jul 07 05:31:00 PM PDT 24
Finished Jul 07 05:49:00 PM PDT 24
Peak memory 729604 kb
Host smart-ce208272-b861-4fd7-a9be-3a9cf7cca096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734176583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2734176583
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3184716744
Short name T481
Test name
Test status
Simulation time 11144309173 ps
CPU time 144.73 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:33:34 PM PDT 24
Peak memory 200232 kb
Host smart-6b7dbe9d-428f-45e4-9363-890a97dd232c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184716744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3184716744
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.603347841
Short name T451
Test name
Test status
Simulation time 19254522233 ps
CPU time 67.74 seconds
Started Jul 07 05:31:07 PM PDT 24
Finished Jul 07 05:32:15 PM PDT 24
Peak memory 200660 kb
Host smart-dfbc5cb7-1131-48e2-82ff-d6093f62e733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603347841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.603347841
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.596328732
Short name T258
Test name
Test status
Simulation time 1955978172 ps
CPU time 11.06 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:31:20 PM PDT 24
Peak memory 200316 kb
Host smart-2e53b143-e0e7-4267-9174-15190a153464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596328732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.596328732
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3290680008
Short name T440
Test name
Test status
Simulation time 1589068130 ps
CPU time 84.58 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:32:31 PM PDT 24
Peak memory 200320 kb
Host smart-036a2c73-25b8-4871-98c0-a1b00631713b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290680008 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3290680008
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.706660690
Short name T408
Test name
Test status
Simulation time 1643586794 ps
CPU time 84.91 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:32:35 PM PDT 24
Peak memory 200288 kb
Host smart-310536ed-cf88-45b3-8241-cfd3738b6867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706660690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.706660690
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1364405631
Short name T278
Test name
Test status
Simulation time 14828671 ps
CPU time 0.6 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:31:09 PM PDT 24
Peak memory 196060 kb
Host smart-722bc9dd-7200-47d2-b43c-c8a91df4628a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364405631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1364405631
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1872427768
Short name T14
Test name
Test status
Simulation time 1926031171 ps
CPU time 27.35 seconds
Started Jul 07 05:31:05 PM PDT 24
Finished Jul 07 05:31:33 PM PDT 24
Peak memory 200292 kb
Host smart-d58f827b-ddf6-4717-8684-342e7c9306b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872427768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1872427768
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1559667177
Short name T190
Test name
Test status
Simulation time 598114264 ps
CPU time 12.02 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:31:24 PM PDT 24
Peak memory 200300 kb
Host smart-d02342b5-2176-4efb-9ead-e4c744d8ab0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559667177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1559667177
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3077704783
Short name T457
Test name
Test status
Simulation time 36151728765 ps
CPU time 653.69 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:41:59 PM PDT 24
Peak memory 730080 kb
Host smart-55f2dd4d-155a-482c-838c-25ddc1ea724a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077704783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3077704783
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1322581996
Short name T526
Test name
Test status
Simulation time 27435236985 ps
CPU time 127.09 seconds
Started Jul 07 05:31:14 PM PDT 24
Finished Jul 07 05:33:21 PM PDT 24
Peak memory 200328 kb
Host smart-2d6700a5-be0a-4905-b93d-3c33b344509d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322581996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1322581996
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1914905706
Short name T447
Test name
Test status
Simulation time 1777933818 ps
CPU time 34.26 seconds
Started Jul 07 05:31:05 PM PDT 24
Finished Jul 07 05:31:40 PM PDT 24
Peak memory 200292 kb
Host smart-56024d5b-2e61-4c72-9104-ca03965c40a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914905706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1914905706
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3700368462
Short name T206
Test name
Test status
Simulation time 201330385 ps
CPU time 5.08 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:31:12 PM PDT 24
Peak memory 200316 kb
Host smart-8b3958a5-fdc4-4e85-92b6-71abfddd2238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700368462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3700368462
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1748535153
Short name T272
Test name
Test status
Simulation time 492475708860 ps
CPU time 3213.53 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 06:24:42 PM PDT 24
Peak memory 807176 kb
Host smart-042c6906-38bf-4c37-835e-fa3fc4cad7ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748535153 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1748535153
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1263085863
Short name T11
Test name
Test status
Simulation time 15275979221 ps
CPU time 77.15 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:32:28 PM PDT 24
Peak memory 200372 kb
Host smart-c705ff6a-7ae7-4e15-8719-40791ecc4afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263085863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1263085863
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2775481901
Short name T488
Test name
Test status
Simulation time 19848974 ps
CPU time 0.58 seconds
Started Jul 07 05:30:46 PM PDT 24
Finished Jul 07 05:30:46 PM PDT 24
Peak memory 196204 kb
Host smart-c2769615-da12-43a9-9196-b0b6d2e5f5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775481901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2775481901
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1751780308
Short name T142
Test name
Test status
Simulation time 2321301326 ps
CPU time 32.01 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:31:35 PM PDT 24
Peak memory 200348 kb
Host smart-54ab7b47-5f66-4ed2-a2f8-75b376d4dcec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751780308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1751780308
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1560578
Short name T342
Test name
Test status
Simulation time 4560398125 ps
CPU time 62.77 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:31:53 PM PDT 24
Peak memory 200392 kb
Host smart-80af5c9d-e135-497c-8f5d-b1042535ddc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1560578
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.4064896625
Short name T467
Test name
Test status
Simulation time 9105659889 ps
CPU time 334.8 seconds
Started Jul 07 05:30:58 PM PDT 24
Finished Jul 07 05:36:33 PM PDT 24
Peak memory 454056 kb
Host smart-10e83c80-65fb-4d56-8472-4f51ce36ed5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064896625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.4064896625
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2983573877
Short name T177
Test name
Test status
Simulation time 3643943582 ps
CPU time 199.5 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:34:08 PM PDT 24
Peak memory 200340 kb
Host smart-fd1b7302-458a-477f-9b10-fad1a94c1874
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983573877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2983573877
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2361589765
Short name T510
Test name
Test status
Simulation time 3407800694 ps
CPU time 44.23 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:31:48 PM PDT 24
Peak memory 200364 kb
Host smart-8086e992-83d5-489f-941c-47c057ff5388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361589765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2361589765
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1329714668
Short name T64
Test name
Test status
Simulation time 65409799 ps
CPU time 0.95 seconds
Started Jul 07 05:30:50 PM PDT 24
Finished Jul 07 05:30:52 PM PDT 24
Peak memory 219248 kb
Host smart-66aa8b24-d825-413d-a261-c249ed429c20
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329714668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1329714668
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1377921172
Short name T458
Test name
Test status
Simulation time 850581026 ps
CPU time 14.73 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:31:03 PM PDT 24
Peak memory 200284 kb
Host smart-4c2935da-cf01-47da-b95b-5ddf7b4249b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377921172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1377921172
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.531163699
Short name T316
Test name
Test status
Simulation time 72410615605 ps
CPU time 874.46 seconds
Started Jul 07 05:30:56 PM PDT 24
Finished Jul 07 05:45:31 PM PDT 24
Peak memory 665148 kb
Host smart-dc2d20e5-5421-4b5e-b9b2-a2a5423c4514
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531163699 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.531163699
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1243564524
Short name T33
Test name
Test status
Simulation time 125997732411 ps
CPU time 388.84 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:37:13 PM PDT 24
Peak memory 264068 kb
Host smart-096583be-f72b-48ae-a1cd-084bcdd683bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243564524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1243564524
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3532511141
Short name T161
Test name
Test status
Simulation time 28708256324 ps
CPU time 83.4 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:32:19 PM PDT 24
Peak memory 200324 kb
Host smart-1bda5899-3b2a-4e61-8192-2e4a41b17efb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3532511141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3532511141
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1669574103
Short name T91
Test name
Test status
Simulation time 16486411078 ps
CPU time 101.64 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:32:29 PM PDT 24
Peak memory 200352 kb
Host smart-1a779691-c839-48bd-8f75-d2d6aea3787f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1669574103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1669574103
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.2399554220
Short name T207
Test name
Test status
Simulation time 3183137513 ps
CPU time 130.34 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:32:59 PM PDT 24
Peak memory 200312 kb
Host smart-ace6b808-fc1e-4c9c-afd7-0a78e7476d77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2399554220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2399554220
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2917710335
Short name T348
Test name
Test status
Simulation time 50389150089 ps
CPU time 607.33 seconds
Started Jul 07 05:30:44 PM PDT 24
Finished Jul 07 05:40:52 PM PDT 24
Peak memory 200304 kb
Host smart-343184c6-a881-4771-878f-d087492ffe52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2917710335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2917710335
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.574176893
Short name T134
Test name
Test status
Simulation time 41981847675 ps
CPU time 2346.88 seconds
Started Jul 07 05:30:58 PM PDT 24
Finished Jul 07 06:10:06 PM PDT 24
Peak memory 216340 kb
Host smart-d5be3673-ece2-43ac-864d-7b92579487f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=574176893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.574176893
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1568925881
Short name T230
Test name
Test status
Simulation time 512931740707 ps
CPU time 2328.74 seconds
Started Jul 07 05:30:48 PM PDT 24
Finished Jul 07 06:09:38 PM PDT 24
Peak memory 215800 kb
Host smart-a4f30b4c-414d-4bb1-9c88-83ec28ee85a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1568925881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1568925881
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3499747737
Short name T366
Test name
Test status
Simulation time 5959403185 ps
CPU time 80.11 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:32:04 PM PDT 24
Peak memory 200400 kb
Host smart-a00009b5-3bdd-4d09-a1b1-39a6339ec7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499747737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3499747737
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1277245958
Short name T295
Test name
Test status
Simulation time 23780737 ps
CPU time 0.6 seconds
Started Jul 07 05:31:09 PM PDT 24
Finished Jul 07 05:31:10 PM PDT 24
Peak memory 196168 kb
Host smart-069d8cfc-38fb-46f4-b965-fac59e9694b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277245958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1277245958
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.934803791
Short name T56
Test name
Test status
Simulation time 774499468 ps
CPU time 48.34 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:32:00 PM PDT 24
Peak memory 200352 kb
Host smart-df72c5b1-783e-4b45-9194-e3e2f986c8ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934803791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.934803791
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1877610438
Short name T444
Test name
Test status
Simulation time 4935287026 ps
CPU time 16.34 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:31:24 PM PDT 24
Peak memory 200352 kb
Host smart-2ca94bcb-79d5-431a-8ac3-343486149730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877610438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1877610438
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1862943805
Short name T321
Test name
Test status
Simulation time 23723045581 ps
CPU time 1475.68 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:55:40 PM PDT 24
Peak memory 758156 kb
Host smart-8c661152-a3e2-4ab2-8c2f-6f4dd2ac81af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862943805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1862943805
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2064829164
Short name T264
Test name
Test status
Simulation time 11522342726 ps
CPU time 183.83 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:34:12 PM PDT 24
Peak memory 200432 kb
Host smart-2047a27a-8a8b-4a79-b4b8-e9fb6972c837
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064829164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2064829164
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3759985187
Short name T251
Test name
Test status
Simulation time 22189606228 ps
CPU time 99.62 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:32:50 PM PDT 24
Peak memory 200340 kb
Host smart-1872e793-b9c5-453d-9f34-cc92c3102df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759985187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3759985187
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.432400574
Short name T359
Test name
Test status
Simulation time 3502502823 ps
CPU time 7.47 seconds
Started Jul 07 05:31:05 PM PDT 24
Finished Jul 07 05:31:13 PM PDT 24
Peak memory 200352 kb
Host smart-6a0f254c-2476-4df1-aaea-e48809933c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432400574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.432400574
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3268140772
Short name T482
Test name
Test status
Simulation time 10149580127 ps
CPU time 131.98 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:33:18 PM PDT 24
Peak memory 200308 kb
Host smart-3ac04cc7-9dfe-4bd4-949a-cebee286145d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268140772 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3268140772
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.949219755
Short name T214
Test name
Test status
Simulation time 680192061 ps
CPU time 4.71 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:31:15 PM PDT 24
Peak memory 200288 kb
Host smart-2a3df169-1c55-4625-94cd-39a606146aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949219755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.949219755
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.234681753
Short name T350
Test name
Test status
Simulation time 87312612 ps
CPU time 0.61 seconds
Started Jul 07 05:31:16 PM PDT 24
Finished Jul 07 05:31:17 PM PDT 24
Peak memory 196804 kb
Host smart-bc497783-6bca-49f8-8f27-5254bf24e71f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234681753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.234681753
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1678312220
Short name T203
Test name
Test status
Simulation time 210262971 ps
CPU time 2.1 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:31:11 PM PDT 24
Peak memory 200292 kb
Host smart-58ed19b6-6775-4797-b1ee-6c94e4e20d70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678312220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1678312220
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1760942822
Short name T193
Test name
Test status
Simulation time 52400904381 ps
CPU time 50.92 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:32:02 PM PDT 24
Peak memory 208548 kb
Host smart-15d82a3c-de81-4ccd-b785-d01b1901d4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760942822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1760942822
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2518066253
Short name T194
Test name
Test status
Simulation time 5350768140 ps
CPU time 139.9 seconds
Started Jul 07 05:31:09 PM PDT 24
Finished Jul 07 05:33:30 PM PDT 24
Peak memory 577936 kb
Host smart-a5eebc64-172d-4fa4-a30c-4ce75636589c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518066253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2518066253
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1566090242
Short name T7
Test name
Test status
Simulation time 60347086080 ps
CPU time 121.28 seconds
Started Jul 07 05:31:18 PM PDT 24
Finished Jul 07 05:33:19 PM PDT 24
Peak memory 200344 kb
Host smart-01d5da9f-edc4-4544-81fd-49b39679f538
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566090242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1566090242
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1897888788
Short name T172
Test name
Test status
Simulation time 8099178664 ps
CPU time 153.14 seconds
Started Jul 07 05:31:17 PM PDT 24
Finished Jul 07 05:33:50 PM PDT 24
Peak memory 200408 kb
Host smart-4e730de0-950a-4527-80ae-d005a4715e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897888788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1897888788
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2083282773
Short name T485
Test name
Test status
Simulation time 674427843 ps
CPU time 3.05 seconds
Started Jul 07 05:31:05 PM PDT 24
Finished Jul 07 05:31:09 PM PDT 24
Peak memory 200332 kb
Host smart-ee11c9d7-7b35-47d4-a9ae-6e3e933f7a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083282773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2083282773
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3099211146
Short name T333
Test name
Test status
Simulation time 107151903742 ps
CPU time 703.74 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:42:55 PM PDT 24
Peak memory 200352 kb
Host smart-d13b3cfc-f584-4493-b592-9131e9300c58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099211146 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3099211146
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2114462121
Short name T490
Test name
Test status
Simulation time 20184201183 ps
CPU time 83.48 seconds
Started Jul 07 05:31:23 PM PDT 24
Finished Jul 07 05:32:47 PM PDT 24
Peak memory 200380 kb
Host smart-10926a2b-ff11-4a27-a580-f3fa2c5db9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114462121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2114462121
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3266421308
Short name T357
Test name
Test status
Simulation time 100234536 ps
CPU time 0.63 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:31:12 PM PDT 24
Peak memory 196180 kb
Host smart-736d4d66-47dd-430c-b6c6-ec480df6c631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266421308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3266421308
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2320763078
Short name T54
Test name
Test status
Simulation time 8552517691 ps
CPU time 28.91 seconds
Started Jul 07 05:31:14 PM PDT 24
Finished Jul 07 05:31:43 PM PDT 24
Peak memory 200328 kb
Host smart-23313334-3cde-4460-9a10-a4a240617593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320763078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2320763078
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2383622893
Short name T505
Test name
Test status
Simulation time 140533488 ps
CPU time 6.69 seconds
Started Jul 07 05:31:12 PM PDT 24
Finished Jul 07 05:31:19 PM PDT 24
Peak memory 200276 kb
Host smart-1efb1d5f-b07d-45f4-8653-0fb76d6a3f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383622893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2383622893
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.713849875
Short name T171
Test name
Test status
Simulation time 23321597 ps
CPU time 0.96 seconds
Started Jul 07 05:31:23 PM PDT 24
Finished Jul 07 05:31:24 PM PDT 24
Peak memory 199944 kb
Host smart-b9b32e6e-c4a6-45c5-a7ee-c865c5081dbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713849875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.713849875
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3337118583
Short name T275
Test name
Test status
Simulation time 15288020943 ps
CPU time 197.77 seconds
Started Jul 07 05:31:15 PM PDT 24
Finished Jul 07 05:34:32 PM PDT 24
Peak memory 200668 kb
Host smart-ecc388cb-f28f-41af-a07a-09e50231ea61
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337118583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3337118583
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1433405203
Short name T327
Test name
Test status
Simulation time 1608262184 ps
CPU time 20.27 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:31:31 PM PDT 24
Peak memory 200336 kb
Host smart-9862659d-ba81-4b89-b678-1dc54b0ad89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433405203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1433405203
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.591375911
Short name T402
Test name
Test status
Simulation time 153815084 ps
CPU time 7.17 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:31:18 PM PDT 24
Peak memory 200288 kb
Host smart-6aa8bf7c-5413-4b4f-9910-37f86146e215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591375911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.591375911
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.4131749130
Short name T486
Test name
Test status
Simulation time 5286768968 ps
CPU time 99.64 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:32:51 PM PDT 24
Peak memory 200368 kb
Host smart-07610f69-2710-4946-8cf3-8cf3f152d5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131749130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.4131749130
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2276986973
Short name T224
Test name
Test status
Simulation time 31202013 ps
CPU time 0.62 seconds
Started Jul 07 05:31:18 PM PDT 24
Finished Jul 07 05:31:18 PM PDT 24
Peak memory 196868 kb
Host smart-8eb001f4-0557-496a-8553-dde81f6aa7f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276986973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2276986973
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1088908364
Short name T331
Test name
Test status
Simulation time 622450893 ps
CPU time 38.16 seconds
Started Jul 07 05:31:26 PM PDT 24
Finished Jul 07 05:32:05 PM PDT 24
Peak memory 200288 kb
Host smart-9095b7ad-b74d-422a-96c7-5016c1a1c6e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088908364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1088908364
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1762695991
Short name T268
Test name
Test status
Simulation time 175587535 ps
CPU time 9.57 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:31:21 PM PDT 24
Peak memory 200304 kb
Host smart-d09a1e49-63ed-4d15-8649-539d8631be83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762695991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1762695991
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.4270968612
Short name T227
Test name
Test status
Simulation time 21786511653 ps
CPU time 965.23 seconds
Started Jul 07 05:31:14 PM PDT 24
Finished Jul 07 05:47:19 PM PDT 24
Peak memory 730996 kb
Host smart-5065a05f-021d-45da-88f8-cbd74f6a321a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270968612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.4270968612
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3248597187
Short name T200
Test name
Test status
Simulation time 8066153635 ps
CPU time 80.73 seconds
Started Jul 07 05:31:18 PM PDT 24
Finished Jul 07 05:32:39 PM PDT 24
Peak memory 200352 kb
Host smart-030a1266-8726-4256-bc6a-cfc557e6b950
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248597187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3248597187
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2698803671
Short name T235
Test name
Test status
Simulation time 3462073379 ps
CPU time 64.02 seconds
Started Jul 07 05:31:22 PM PDT 24
Finished Jul 07 05:32:27 PM PDT 24
Peak memory 200316 kb
Host smart-e1c20d06-de59-4342-aa7c-f61a93b259d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698803671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2698803671
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3420400533
Short name T68
Test name
Test status
Simulation time 1290958724 ps
CPU time 17.74 seconds
Started Jul 07 05:31:17 PM PDT 24
Finished Jul 07 05:31:35 PM PDT 24
Peak memory 200344 kb
Host smart-32072ab4-41e4-4e47-9272-87472efc9274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420400533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3420400533
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.452514955
Short name T523
Test name
Test status
Simulation time 17811992083 ps
CPU time 109.57 seconds
Started Jul 07 05:31:13 PM PDT 24
Finished Jul 07 05:33:03 PM PDT 24
Peak memory 200420 kb
Host smart-6cb6237d-b78f-4541-9ac4-8b42ada282bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452514955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.452514955
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2796784083
Short name T188
Test name
Test status
Simulation time 18694457 ps
CPU time 0.59 seconds
Started Jul 07 05:31:19 PM PDT 24
Finished Jul 07 05:31:20 PM PDT 24
Peak memory 196196 kb
Host smart-389f109a-8d93-40b2-8817-960ef4349ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796784083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2796784083
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1195682102
Short name T13
Test name
Test status
Simulation time 4165593046 ps
CPU time 61.94 seconds
Started Jul 07 05:31:21 PM PDT 24
Finished Jul 07 05:32:23 PM PDT 24
Peak memory 200316 kb
Host smart-64def328-7800-488c-8a66-2c52c3a6957f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1195682102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1195682102
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2298532217
Short name T382
Test name
Test status
Simulation time 1857910173 ps
CPU time 37.64 seconds
Started Jul 07 05:31:20 PM PDT 24
Finished Jul 07 05:31:58 PM PDT 24
Peak memory 200232 kb
Host smart-f32c8277-a1cb-43d8-8134-bf5ed92dc18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298532217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2298532217
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2507355701
Short name T232
Test name
Test status
Simulation time 4821336849 ps
CPU time 837.31 seconds
Started Jul 07 05:31:17 PM PDT 24
Finished Jul 07 05:45:20 PM PDT 24
Peak memory 516240 kb
Host smart-cd3fd161-290b-43df-b258-e9c83c77a05f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507355701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2507355701
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3460280761
Short name T222
Test name
Test status
Simulation time 1934072913 ps
CPU time 55.96 seconds
Started Jul 07 05:31:21 PM PDT 24
Finished Jul 07 05:32:17 PM PDT 24
Peak memory 200336 kb
Host smart-b104b014-4a39-411b-8f45-a9105604cfbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460280761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3460280761
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1196339489
Short name T170
Test name
Test status
Simulation time 4710912889 ps
CPU time 124.67 seconds
Started Jul 07 05:31:22 PM PDT 24
Finished Jul 07 05:33:27 PM PDT 24
Peak memory 208588 kb
Host smart-93990435-bf15-4d16-9ef8-9977c07adadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196339489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1196339489
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.938004914
Short name T472
Test name
Test status
Simulation time 96561655 ps
CPU time 2.76 seconds
Started Jul 07 05:31:11 PM PDT 24
Finished Jul 07 05:31:15 PM PDT 24
Peak memory 200340 kb
Host smart-505b01b3-d6fa-4fb5-a372-95c55c5506fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938004914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.938004914
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1558675295
Short name T420
Test name
Test status
Simulation time 65511016260 ps
CPU time 1132.4 seconds
Started Jul 07 05:31:19 PM PDT 24
Finished Jul 07 05:50:11 PM PDT 24
Peak memory 208580 kb
Host smart-8bdf72b6-b6cd-488e-93bf-0d5d604bd97f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558675295 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1558675295
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3985389990
Short name T297
Test name
Test status
Simulation time 2783673840 ps
CPU time 38.66 seconds
Started Jul 07 05:31:16 PM PDT 24
Finished Jul 07 05:31:55 PM PDT 24
Peak memory 200412 kb
Host smart-a7e27cda-82e1-47c5-89e2-fe546990afab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985389990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3985389990
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.921060170
Short name T274
Test name
Test status
Simulation time 14427963 ps
CPU time 0.61 seconds
Started Jul 07 05:31:18 PM PDT 24
Finished Jul 07 05:31:19 PM PDT 24
Peak memory 195840 kb
Host smart-e9bc4b16-38a0-47ae-9793-33bc94334762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921060170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.921060170
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2221635837
Short name T284
Test name
Test status
Simulation time 5653493888 ps
CPU time 33.09 seconds
Started Jul 07 05:31:21 PM PDT 24
Finished Jul 07 05:31:54 PM PDT 24
Peak memory 200396 kb
Host smart-54735c99-1b74-4327-b874-2c5e09ca76e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2221635837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2221635837
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3884475078
Short name T435
Test name
Test status
Simulation time 991802981 ps
CPU time 19.34 seconds
Started Jul 07 05:31:17 PM PDT 24
Finished Jul 07 05:31:37 PM PDT 24
Peak memory 200356 kb
Host smart-b0592614-cd02-484d-a3e2-adab1149868e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884475078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3884475078
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.66407611
Short name T322
Test name
Test status
Simulation time 52459566 ps
CPU time 1.04 seconds
Started Jul 07 05:31:25 PM PDT 24
Finished Jul 07 05:31:26 PM PDT 24
Peak memory 208428 kb
Host smart-2b0ff968-8d54-4bc4-aeec-863a29738d92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66407611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.66407611
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2039373618
Short name T90
Test name
Test status
Simulation time 43921021794 ps
CPU time 152.33 seconds
Started Jul 07 05:31:24 PM PDT 24
Finished Jul 07 05:33:57 PM PDT 24
Peak memory 200432 kb
Host smart-1f383021-1f5e-4ee8-b851-c992a030f93e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039373618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2039373618
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2027934722
Short name T383
Test name
Test status
Simulation time 2613509205 ps
CPU time 153.16 seconds
Started Jul 07 05:31:22 PM PDT 24
Finished Jul 07 05:33:56 PM PDT 24
Peak memory 200336 kb
Host smart-517731e4-a79c-4db3-b3ba-e97075cebb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027934722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2027934722
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2364333857
Short name T365
Test name
Test status
Simulation time 7512958336 ps
CPU time 10.08 seconds
Started Jul 07 05:31:20 PM PDT 24
Finished Jul 07 05:31:30 PM PDT 24
Peak memory 200340 kb
Host smart-cd2b04cf-152c-4f88-a5ea-d165118848ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364333857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2364333857
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1733269086
Short name T93
Test name
Test status
Simulation time 143196582019 ps
CPU time 1314.77 seconds
Started Jul 07 05:31:17 PM PDT 24
Finished Jul 07 05:53:12 PM PDT 24
Peak memory 324932 kb
Host smart-1de252fa-a89c-4f53-9d04-215dfec11f45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733269086 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1733269086
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2058853396
Short name T121
Test name
Test status
Simulation time 1450230182 ps
CPU time 63.76 seconds
Started Jul 07 05:31:25 PM PDT 24
Finished Jul 07 05:32:30 PM PDT 24
Peak memory 200284 kb
Host smart-3200f2da-c43d-4068-9963-c9e7c36d27dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058853396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2058853396
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1386930195
Short name T292
Test name
Test status
Simulation time 19269521 ps
CPU time 0.58 seconds
Started Jul 07 05:31:21 PM PDT 24
Finished Jul 07 05:31:22 PM PDT 24
Peak memory 196200 kb
Host smart-8ea153fa-504a-4d2f-83e7-9d14ebf5a14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386930195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1386930195
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.425098126
Short name T36
Test name
Test status
Simulation time 2694282752 ps
CPU time 71.15 seconds
Started Jul 07 05:31:23 PM PDT 24
Finished Jul 07 05:32:34 PM PDT 24
Peak memory 200368 kb
Host smart-563285fd-dd96-48d8-a668-a8bff2ab11cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=425098126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.425098126
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2463193810
Short name T72
Test name
Test status
Simulation time 1970185334 ps
CPU time 33.05 seconds
Started Jul 07 05:31:18 PM PDT 24
Finished Jul 07 05:31:51 PM PDT 24
Peak memory 200192 kb
Host smart-5160f5a4-bcfb-473f-99b9-d0a4b64e7895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463193810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2463193810
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1891120745
Short name T349
Test name
Test status
Simulation time 1203088449 ps
CPU time 8.24 seconds
Started Jul 07 05:31:23 PM PDT 24
Finished Jul 07 05:31:31 PM PDT 24
Peak memory 201896 kb
Host smart-c595b540-8d01-41e1-a6ab-cfb6ebcf27ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1891120745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1891120745
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.125960504
Short name T500
Test name
Test status
Simulation time 13386428728 ps
CPU time 59.31 seconds
Started Jul 07 05:31:19 PM PDT 24
Finished Jul 07 05:32:19 PM PDT 24
Peak memory 200332 kb
Host smart-2a645af8-3037-44f3-a5f3-5ad07ffdcf41
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125960504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.125960504
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.4053663502
Short name T385
Test name
Test status
Simulation time 19692404969 ps
CPU time 264.86 seconds
Started Jul 07 05:31:23 PM PDT 24
Finished Jul 07 05:35:48 PM PDT 24
Peak memory 200456 kb
Host smart-92f5081e-69fb-4e08-9ba7-44d9495ccfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053663502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4053663502
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2948437672
Short name T141
Test name
Test status
Simulation time 719863500 ps
CPU time 3.18 seconds
Started Jul 07 05:31:25 PM PDT 24
Finished Jul 07 05:31:29 PM PDT 24
Peak memory 200288 kb
Host smart-f68b27d6-70a5-4df7-88cd-e447f0980cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948437672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2948437672
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3652082176
Short name T310
Test name
Test status
Simulation time 4647786292 ps
CPU time 215.99 seconds
Started Jul 07 05:31:20 PM PDT 24
Finished Jul 07 05:34:57 PM PDT 24
Peak memory 200628 kb
Host smart-bffc51e8-f2e8-4c7f-836d-9761baa2dc8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652082176 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3652082176
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2039247923
Short name T202
Test name
Test status
Simulation time 997912917 ps
CPU time 25.36 seconds
Started Jul 07 05:31:26 PM PDT 24
Finished Jul 07 05:31:52 PM PDT 24
Peak memory 200348 kb
Host smart-4886a7c0-1d4f-49b4-b7fa-ee2a7236c875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039247923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2039247923
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.484503565
Short name T356
Test name
Test status
Simulation time 18527294 ps
CPU time 0.56 seconds
Started Jul 07 05:31:20 PM PDT 24
Finished Jul 07 05:31:21 PM PDT 24
Peak memory 195156 kb
Host smart-1c329f0c-bd14-4c03-9f43-70c6a3127557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484503565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.484503565
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2145920492
Short name T361
Test name
Test status
Simulation time 3190858749 ps
CPU time 97.71 seconds
Started Jul 07 05:31:26 PM PDT 24
Finished Jul 07 05:33:04 PM PDT 24
Peak memory 200348 kb
Host smart-38529a7b-91cc-42cf-a26b-4a3bad9f8c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145920492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2145920492
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.959076341
Short name T145
Test name
Test status
Simulation time 1274534532 ps
CPU time 35.08 seconds
Started Jul 07 05:31:20 PM PDT 24
Finished Jul 07 05:31:56 PM PDT 24
Peak memory 200200 kb
Host smart-49f7b8e6-e1cb-4b12-bdcd-2d9dfa1f97d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959076341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.959076341
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3755172365
Short name T477
Test name
Test status
Simulation time 3686263875 ps
CPU time 64.59 seconds
Started Jul 07 05:31:25 PM PDT 24
Finished Jul 07 05:32:31 PM PDT 24
Peak memory 347968 kb
Host smart-28088442-9486-448a-af9b-a139d93b3058
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755172365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3755172365
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2293886299
Short name T303
Test name
Test status
Simulation time 3144202205 ps
CPU time 152.18 seconds
Started Jul 07 05:31:21 PM PDT 24
Finished Jul 07 05:33:53 PM PDT 24
Peak memory 200380 kb
Host smart-d740259c-f2e5-422a-a719-44fce1b45452
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293886299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2293886299
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1697485451
Short name T521
Test name
Test status
Simulation time 459856490 ps
CPU time 8.65 seconds
Started Jul 07 05:31:23 PM PDT 24
Finished Jul 07 05:31:32 PM PDT 24
Peak memory 200236 kb
Host smart-5dbe9db6-fe3b-484f-8168-2aff6d7e51a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697485451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1697485451
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3263296980
Short name T479
Test name
Test status
Simulation time 36149362 ps
CPU time 0.97 seconds
Started Jul 07 05:31:25 PM PDT 24
Finished Jul 07 05:31:27 PM PDT 24
Peak memory 199928 kb
Host smart-9c51e7f3-09df-4180-8edd-c79edefc8f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263296980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3263296980
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3585703956
Short name T456
Test name
Test status
Simulation time 44049829620 ps
CPU time 920.32 seconds
Started Jul 07 05:31:23 PM PDT 24
Finished Jul 07 05:46:44 PM PDT 24
Peak memory 670224 kb
Host smart-54d6d128-eefb-4700-8384-9b1aa4824e09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585703956 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3585703956
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.249655982
Short name T466
Test name
Test status
Simulation time 5418721799 ps
CPU time 47.7 seconds
Started Jul 07 05:31:21 PM PDT 24
Finished Jul 07 05:32:09 PM PDT 24
Peak memory 200368 kb
Host smart-907a88f6-c680-42de-8e4b-3680ca085030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249655982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.249655982
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2038652657
Short name T241
Test name
Test status
Simulation time 21709379 ps
CPU time 0.56 seconds
Started Jul 07 05:31:33 PM PDT 24
Finished Jul 07 05:31:34 PM PDT 24
Peak memory 195840 kb
Host smart-20194a9c-ba60-435d-adeb-fff9b61cdba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038652657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2038652657
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1083042807
Short name T494
Test name
Test status
Simulation time 44478336 ps
CPU time 2.39 seconds
Started Jul 07 05:31:23 PM PDT 24
Finished Jul 07 05:31:26 PM PDT 24
Peak memory 200292 kb
Host smart-c96a3a9e-e696-43c5-94ca-c6ebf2fd0d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083042807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1083042807
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.278877106
Short name T376
Test name
Test status
Simulation time 2872681462 ps
CPU time 43.32 seconds
Started Jul 07 05:31:27 PM PDT 24
Finished Jul 07 05:32:11 PM PDT 24
Peak memory 200384 kb
Host smart-86e0262f-3ef9-41f0-8509-d20589a6be79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278877106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.278877106
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2347202503
Short name T462
Test name
Test status
Simulation time 5565687454 ps
CPU time 1022.01 seconds
Started Jul 07 05:31:26 PM PDT 24
Finished Jul 07 05:48:29 PM PDT 24
Peak memory 732388 kb
Host smart-66572acb-eb4c-41a6-9918-885ea655e8cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347202503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2347202503
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.96542950
Short name T256
Test name
Test status
Simulation time 44754987021 ps
CPU time 181.46 seconds
Started Jul 07 05:31:26 PM PDT 24
Finished Jul 07 05:34:28 PM PDT 24
Peak memory 200344 kb
Host smart-085eebe1-a8ee-4edd-96fd-d8ccfe1d0ee6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96542950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.96542950
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.115227433
Short name T443
Test name
Test status
Simulation time 9431342256 ps
CPU time 86.09 seconds
Started Jul 07 05:31:26 PM PDT 24
Finished Jul 07 05:32:53 PM PDT 24
Peak memory 200572 kb
Host smart-e50510ac-d82b-4a67-804e-2417cae290eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115227433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.115227433
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2061961112
Short name T513
Test name
Test status
Simulation time 673615874 ps
CPU time 11.19 seconds
Started Jul 07 05:31:28 PM PDT 24
Finished Jul 07 05:31:39 PM PDT 24
Peak memory 200308 kb
Host smart-3264ad9a-4932-4ef3-ba54-8cd9910ba0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061961112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2061961112
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3523281433
Short name T83
Test name
Test status
Simulation time 109335960981 ps
CPU time 3072.42 seconds
Started Jul 07 05:31:22 PM PDT 24
Finished Jul 07 06:22:35 PM PDT 24
Peak memory 791736 kb
Host smart-8f1903da-8a2a-4c4a-8872-a1ed18a44651
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523281433 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3523281433
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4075685624
Short name T122
Test name
Test status
Simulation time 27504017260 ps
CPU time 94.15 seconds
Started Jul 07 05:31:22 PM PDT 24
Finished Jul 07 05:32:56 PM PDT 24
Peak memory 200628 kb
Host smart-f77cdcf3-e41c-4c6f-ad28-0e51197043ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075685624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4075685624
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1561719328
Short name T288
Test name
Test status
Simulation time 26747136 ps
CPU time 0.57 seconds
Started Jul 07 05:31:28 PM PDT 24
Finished Jul 07 05:31:29 PM PDT 24
Peak memory 196220 kb
Host smart-ac022d05-827d-415a-912f-6c919d9a4ba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561719328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1561719328
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1193167133
Short name T201
Test name
Test status
Simulation time 139286032 ps
CPU time 2.03 seconds
Started Jul 07 05:31:27 PM PDT 24
Finished Jul 07 05:31:29 PM PDT 24
Peak memory 200240 kb
Host smart-d0fb6832-9f07-407e-b20b-0b89b6906168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193167133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1193167133
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3424269160
Short name T219
Test name
Test status
Simulation time 1874221459 ps
CPU time 27.05 seconds
Started Jul 07 05:31:24 PM PDT 24
Finished Jul 07 05:31:51 PM PDT 24
Peak memory 200304 kb
Host smart-afb31027-60d4-46db-ac6e-34758cd40433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424269160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3424269160
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3138462959
Short name T473
Test name
Test status
Simulation time 22927252284 ps
CPU time 1047.6 seconds
Started Jul 07 05:31:27 PM PDT 24
Finished Jul 07 05:48:55 PM PDT 24
Peak memory 692776 kb
Host smart-5cbb0240-922a-43de-8bca-ae5c466988e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138462959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3138462959
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3491810870
Short name T73
Test name
Test status
Simulation time 1350229341 ps
CPU time 18.85 seconds
Started Jul 07 05:31:35 PM PDT 24
Finished Jul 07 05:31:54 PM PDT 24
Peak memory 200196 kb
Host smart-63e31c0a-ba09-4780-b613-d07166339e30
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491810870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3491810870
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2910938035
Short name T162
Test name
Test status
Simulation time 13881932448 ps
CPU time 201.19 seconds
Started Jul 07 05:31:35 PM PDT 24
Finished Jul 07 05:34:57 PM PDT 24
Peak memory 200472 kb
Host smart-0dac46cb-fd5c-4066-95c2-6494282cac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910938035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2910938035
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3464843830
Short name T259
Test name
Test status
Simulation time 2683324286 ps
CPU time 12.41 seconds
Started Jul 07 05:31:25 PM PDT 24
Finished Jul 07 05:31:38 PM PDT 24
Peak memory 200412 kb
Host smart-801db564-b9a6-44c0-8ae7-5ff0eb02e78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464843830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3464843830
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.174033340
Short name T424
Test name
Test status
Simulation time 3768899861 ps
CPU time 19.92 seconds
Started Jul 07 05:31:35 PM PDT 24
Finished Jul 07 05:31:56 PM PDT 24
Peak memory 200340 kb
Host smart-50c9639a-7844-4350-8200-6d2dbf6c7ec6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174033340 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.174033340
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3136931982
Short name T95
Test name
Test status
Simulation time 1479708189 ps
CPU time 24.98 seconds
Started Jul 07 05:31:31 PM PDT 24
Finished Jul 07 05:31:57 PM PDT 24
Peak memory 200340 kb
Host smart-d04fe4c7-0c0a-4f34-9c8d-81e13a99ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136931982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3136931982
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2058967286
Short name T455
Test name
Test status
Simulation time 13605115 ps
CPU time 0.58 seconds
Started Jul 07 05:30:54 PM PDT 24
Finished Jul 07 05:30:55 PM PDT 24
Peak memory 195156 kb
Host smart-a57c505f-e253-4fc4-9308-0420edc19ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058967286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2058967286
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.466376602
Short name T305
Test name
Test status
Simulation time 2068034438 ps
CPU time 59.52 seconds
Started Jul 07 05:30:56 PM PDT 24
Finished Jul 07 05:31:56 PM PDT 24
Peak memory 200356 kb
Host smart-2927f975-5298-4a5e-be24-b8df6ee3c266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466376602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.466376602
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3157768493
Short name T343
Test name
Test status
Simulation time 4035671039 ps
CPU time 36.48 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:39 PM PDT 24
Peak memory 200248 kb
Host smart-49ccd172-3a24-4c22-ac2b-d110aeb1ddf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157768493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3157768493
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1488717446
Short name T155
Test name
Test status
Simulation time 12330123637 ps
CPU time 575.68 seconds
Started Jul 07 05:30:48 PM PDT 24
Finished Jul 07 05:40:25 PM PDT 24
Peak memory 711968 kb
Host smart-588b20d3-01a2-4164-b586-21dc5ea24212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488717446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1488717446
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1545840999
Short name T394
Test name
Test status
Simulation time 3943113365 ps
CPU time 211.49 seconds
Started Jul 07 05:31:09 PM PDT 24
Finished Jul 07 05:34:41 PM PDT 24
Peak memory 200236 kb
Host smart-73883f69-5cb2-4f2d-93bb-b357e9b065f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545840999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1545840999
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1069353122
Short name T325
Test name
Test status
Simulation time 5929417702 ps
CPU time 81.99 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:32:12 PM PDT 24
Peak memory 200248 kb
Host smart-87be226c-2dc5-441e-a77b-53f951227ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069353122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1069353122
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3699257421
Short name T63
Test name
Test status
Simulation time 150307225 ps
CPU time 0.83 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:30:57 PM PDT 24
Peak memory 218404 kb
Host smart-1ad944d9-9eed-4bd3-8c9b-0f77682971c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699257421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3699257421
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1668749571
Short name T265
Test name
Test status
Simulation time 595143566 ps
CPU time 7.31 seconds
Started Jul 07 05:30:58 PM PDT 24
Finished Jul 07 05:31:06 PM PDT 24
Peak memory 200288 kb
Host smart-459cd5a8-e53e-4928-9a2f-bab58d24dd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668749571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1668749571
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1443739803
Short name T165
Test name
Test status
Simulation time 22321938843 ps
CPU time 273.82 seconds
Started Jul 07 05:30:54 PM PDT 24
Finished Jul 07 05:35:28 PM PDT 24
Peak memory 200368 kb
Host smart-d2e81f68-b049-41bb-a885-59da1a36371b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443739803 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1443739803
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3018258042
Short name T461
Test name
Test status
Simulation time 68480610988 ps
CPU time 71.43 seconds
Started Jul 07 05:30:56 PM PDT 24
Finished Jul 07 05:32:08 PM PDT 24
Peak memory 200408 kb
Host smart-be7ccede-bf71-4a0d-a514-9bb498b60354
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3018258042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3018258042
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1002509083
Short name T52
Test name
Test status
Simulation time 17868861747 ps
CPU time 70.07 seconds
Started Jul 07 05:30:53 PM PDT 24
Finished Jul 07 05:32:04 PM PDT 24
Peak memory 200324 kb
Host smart-d957f8a8-521c-4c5e-b627-106863b51b7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1002509083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1002509083
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2234793196
Short name T208
Test name
Test status
Simulation time 4961644239 ps
CPU time 71.62 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:32:14 PM PDT 24
Peak memory 200324 kb
Host smart-bc5ab360-ede9-4809-bc53-2b1c5f8a2ccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2234793196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2234793196
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.92302386
Short name T475
Test name
Test status
Simulation time 225444868310 ps
CPU time 676.78 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:42:13 PM PDT 24
Peak memory 200340 kb
Host smart-b24bbd1b-7baf-410f-bbc0-549391aebb84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=92302386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.92302386
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2200663804
Short name T429
Test name
Test status
Simulation time 40005470927 ps
CPU time 2209.98 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 06:07:46 PM PDT 24
Peak memory 216768 kb
Host smart-12df032c-113f-4655-8a83-c862b370bb2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2200663804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2200663804
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.3369424303
Short name T426
Test name
Test status
Simulation time 39826005623 ps
CPU time 2281.19 seconds
Started Jul 07 05:31:00 PM PDT 24
Finished Jul 07 06:09:01 PM PDT 24
Peak memory 216044 kb
Host smart-b60cd5c2-bd7c-4bc3-90fa-61452d5523a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3369424303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.3369424303
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.4130642826
Short name T432
Test name
Test status
Simulation time 3353023883 ps
CPU time 125.51 seconds
Started Jul 07 05:30:51 PM PDT 24
Finished Jul 07 05:32:57 PM PDT 24
Peak memory 200240 kb
Host smart-9bda6dbb-97f5-4300-ac90-e10f2176de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130642826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.4130642826
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.405987654
Short name T185
Test name
Test status
Simulation time 13624788 ps
CPU time 0.58 seconds
Started Jul 07 05:31:29 PM PDT 24
Finished Jul 07 05:31:29 PM PDT 24
Peak memory 195932 kb
Host smart-b2025f33-3c22-47c6-b3b6-6f0eaedbd23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405987654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.405987654
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3382708005
Short name T9
Test name
Test status
Simulation time 3234357794 ps
CPU time 16.99 seconds
Started Jul 07 05:31:30 PM PDT 24
Finished Jul 07 05:31:47 PM PDT 24
Peak memory 200352 kb
Host smart-1108b52b-a655-4e4c-8fbc-9af38e71be24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382708005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3382708005
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.4258278959
Short name T377
Test name
Test status
Simulation time 867124469 ps
CPU time 12.3 seconds
Started Jul 07 05:31:24 PM PDT 24
Finished Jul 07 05:31:37 PM PDT 24
Peak memory 200240 kb
Host smart-f732624a-5bfd-45d6-a996-48345c61b763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258278959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.4258278959
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.688213668
Short name T281
Test name
Test status
Simulation time 3013300522 ps
CPU time 490.14 seconds
Started Jul 07 05:31:30 PM PDT 24
Finished Jul 07 05:39:40 PM PDT 24
Peak memory 704616 kb
Host smart-c3063ece-7dfe-4381-9bef-3ddbe922652b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688213668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.688213668
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3963755507
Short name T335
Test name
Test status
Simulation time 1801636054 ps
CPU time 46.86 seconds
Started Jul 07 05:31:38 PM PDT 24
Finished Jul 07 05:32:25 PM PDT 24
Peak memory 200196 kb
Host smart-60e51315-e25d-4113-a722-ee9607759f56
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963755507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3963755507
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3860637241
Short name T218
Test name
Test status
Simulation time 14214341375 ps
CPU time 167.72 seconds
Started Jul 07 05:31:31 PM PDT 24
Finished Jul 07 05:34:19 PM PDT 24
Peak memory 200388 kb
Host smart-7bbdad12-2d33-4e7a-b8a0-60a3e381d1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860637241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3860637241
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3520041467
Short name T212
Test name
Test status
Simulation time 301296651 ps
CPU time 13.98 seconds
Started Jul 07 05:31:32 PM PDT 24
Finished Jul 07 05:31:46 PM PDT 24
Peak memory 200568 kb
Host smart-84a1c09a-3fea-4f3c-b39b-a7952f5baca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520041467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3520041467
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2645498438
Short name T85
Test name
Test status
Simulation time 249668781201 ps
CPU time 1325.2 seconds
Started Jul 07 05:31:27 PM PDT 24
Finished Jul 07 05:53:32 PM PDT 24
Peak memory 703680 kb
Host smart-bac5a660-e60f-4fde-80a4-67eb23d3b0b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645498438 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2645498438
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2578049745
Short name T368
Test name
Test status
Simulation time 13364675048 ps
CPU time 125.3 seconds
Started Jul 07 05:31:28 PM PDT 24
Finished Jul 07 05:33:34 PM PDT 24
Peak memory 200384 kb
Host smart-9ae73f56-6450-4f86-8745-0ba8c1549f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578049745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2578049745
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3930875186
Short name T279
Test name
Test status
Simulation time 44308073 ps
CPU time 0.58 seconds
Started Jul 07 05:31:30 PM PDT 24
Finished Jul 07 05:31:31 PM PDT 24
Peak memory 195164 kb
Host smart-5945e31c-8284-4a2f-bfb5-3c69b5dd7811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930875186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3930875186
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1983383534
Short name T431
Test name
Test status
Simulation time 7758072850 ps
CPU time 51.41 seconds
Started Jul 07 05:31:26 PM PDT 24
Finished Jul 07 05:32:18 PM PDT 24
Peak memory 200368 kb
Host smart-1ea836ae-6ea8-45e1-b691-4972d672ee42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983383534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1983383534
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.70713085
Short name T29
Test name
Test status
Simulation time 136553878 ps
CPU time 7.18 seconds
Started Jul 07 05:31:29 PM PDT 24
Finished Jul 07 05:31:37 PM PDT 24
Peak memory 200212 kb
Host smart-f6ff892f-22e8-4e81-bf35-f77277f20c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70713085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.70713085
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2961319272
Short name T17
Test name
Test status
Simulation time 2310822504 ps
CPU time 228.82 seconds
Started Jul 07 05:31:26 PM PDT 24
Finished Jul 07 05:35:16 PM PDT 24
Peak memory 613008 kb
Host smart-21dd9481-2a31-4a08-a015-fe06d28011a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961319272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2961319272
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3585187892
Short name T502
Test name
Test status
Simulation time 16366656792 ps
CPU time 209.04 seconds
Started Jul 07 05:31:30 PM PDT 24
Finished Jul 07 05:35:00 PM PDT 24
Peak memory 200428 kb
Host smart-5dcef377-08e4-4d2d-8efc-249e622714ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585187892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3585187892
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3886946317
Short name T324
Test name
Test status
Simulation time 7032781504 ps
CPU time 101.96 seconds
Started Jul 07 05:31:28 PM PDT 24
Finished Jul 07 05:33:10 PM PDT 24
Peak memory 200464 kb
Host smart-3541b156-87f4-4c90-95f9-b09a78a47b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886946317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3886946317
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4199963024
Short name T389
Test name
Test status
Simulation time 176074234 ps
CPU time 8.85 seconds
Started Jul 07 05:31:27 PM PDT 24
Finished Jul 07 05:31:36 PM PDT 24
Peak memory 200368 kb
Host smart-593e9028-f213-48ad-b092-0f5a0c9c46a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199963024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4199963024
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3429875874
Short name T84
Test name
Test status
Simulation time 66141111687 ps
CPU time 822.03 seconds
Started Jul 07 05:31:35 PM PDT 24
Finished Jul 07 05:45:18 PM PDT 24
Peak memory 215952 kb
Host smart-841c7633-38c4-4024-ae54-f591aeab8533
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429875874 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3429875874
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3764944099
Short name T503
Test name
Test status
Simulation time 911158464 ps
CPU time 43.74 seconds
Started Jul 07 05:31:29 PM PDT 24
Finished Jul 07 05:32:13 PM PDT 24
Peak memory 200336 kb
Host smart-c0cea2c4-c2bb-4317-a505-76759f121419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764944099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3764944099
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3191118489
Short name T184
Test name
Test status
Simulation time 40302548 ps
CPU time 0.6 seconds
Started Jul 07 05:31:31 PM PDT 24
Finished Jul 07 05:31:32 PM PDT 24
Peak memory 196192 kb
Host smart-f334efa4-5812-4169-828e-d3bb6cc4b689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191118489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3191118489
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.917107654
Short name T287
Test name
Test status
Simulation time 2798445322 ps
CPU time 39.6 seconds
Started Jul 07 05:31:36 PM PDT 24
Finished Jul 07 05:32:16 PM PDT 24
Peak memory 200372 kb
Host smart-1efb9a82-9322-41d9-8856-72250c41ba19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917107654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.917107654
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3594478192
Short name T340
Test name
Test status
Simulation time 266025005 ps
CPU time 13.7 seconds
Started Jul 07 05:31:31 PM PDT 24
Finished Jul 07 05:31:45 PM PDT 24
Peak memory 200300 kb
Host smart-827fd7b6-c47b-43dc-a24c-726374f77e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594478192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3594478192
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2224849197
Short name T159
Test name
Test status
Simulation time 2367605283 ps
CPU time 391.59 seconds
Started Jul 07 05:31:28 PM PDT 24
Finished Jul 07 05:37:59 PM PDT 24
Peak memory 659108 kb
Host smart-521a78fe-dafa-4707-be48-45231d14c597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224849197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2224849197
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3597581823
Short name T195
Test name
Test status
Simulation time 97799596952 ps
CPU time 165.06 seconds
Started Jul 07 05:31:36 PM PDT 24
Finished Jul 07 05:34:22 PM PDT 24
Peak memory 200308 kb
Host smart-64aa48f0-9682-47f7-a209-60d8cf674827
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597581823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3597581823
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3423985781
Short name T355
Test name
Test status
Simulation time 907546095 ps
CPU time 44.29 seconds
Started Jul 07 05:31:35 PM PDT 24
Finished Jul 07 05:32:19 PM PDT 24
Peak memory 200312 kb
Host smart-45ad97b0-6a66-4028-80db-700bd4c7214a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423985781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3423985781
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1144399322
Short name T306
Test name
Test status
Simulation time 1175748070 ps
CPU time 14.16 seconds
Started Jul 07 05:31:35 PM PDT 24
Finished Jul 07 05:31:49 PM PDT 24
Peak memory 200348 kb
Host smart-dd0573fe-6b15-457a-921e-72edbec8bb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144399322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1144399322
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2428680771
Short name T419
Test name
Test status
Simulation time 2518525908 ps
CPU time 140.42 seconds
Started Jul 07 05:31:34 PM PDT 24
Finished Jul 07 05:33:55 PM PDT 24
Peak memory 200364 kb
Host smart-0250ea2b-bc94-441f-87d2-a788e25c032f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428680771 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2428680771
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2564972103
Short name T439
Test name
Test status
Simulation time 14728114191 ps
CPU time 70.23 seconds
Started Jul 07 05:31:34 PM PDT 24
Finished Jul 07 05:32:44 PM PDT 24
Peak memory 200356 kb
Host smart-977580a0-5d80-4a01-911a-9423b1029f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564972103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2564972103
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2923702180
Short name T237
Test name
Test status
Simulation time 13233785 ps
CPU time 0.6 seconds
Started Jul 07 05:31:38 PM PDT 24
Finished Jul 07 05:31:39 PM PDT 24
Peak memory 195812 kb
Host smart-9e3574ea-b7a5-436a-8ea9-b08181aee4b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923702180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2923702180
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3877060341
Short name T86
Test name
Test status
Simulation time 4971524968 ps
CPU time 72.08 seconds
Started Jul 07 05:31:32 PM PDT 24
Finished Jul 07 05:32:45 PM PDT 24
Peak memory 208548 kb
Host smart-2f6357e9-6789-4612-9b63-baf55883c9e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3877060341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3877060341
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3632644317
Short name T273
Test name
Test status
Simulation time 4459860500 ps
CPU time 65.12 seconds
Started Jul 07 05:31:36 PM PDT 24
Finished Jul 07 05:32:42 PM PDT 24
Peak memory 208512 kb
Host smart-f6be5016-a1eb-44dc-b4d9-c94dd268a2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632644317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3632644317
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3074238548
Short name T16
Test name
Test status
Simulation time 1823836642 ps
CPU time 365.93 seconds
Started Jul 07 05:31:27 PM PDT 24
Finished Jul 07 05:37:33 PM PDT 24
Peak memory 710744 kb
Host smart-9523756a-f9be-4735-be56-bdbfd7cd2172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074238548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3074238548
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1141390514
Short name T404
Test name
Test status
Simulation time 24717910040 ps
CPU time 71.17 seconds
Started Jul 07 05:31:36 PM PDT 24
Finished Jul 07 05:32:47 PM PDT 24
Peak memory 200292 kb
Host smart-d1c8f665-014d-45a5-a72d-7b5f9c8b4840
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141390514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1141390514
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1237950349
Short name T187
Test name
Test status
Simulation time 10090062450 ps
CPU time 177.55 seconds
Started Jul 07 05:31:35 PM PDT 24
Finished Jul 07 05:34:33 PM PDT 24
Peak memory 208584 kb
Host smart-e56f6569-1330-430a-ad52-76dae10901c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237950349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1237950349
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3262285102
Short name T293
Test name
Test status
Simulation time 1319564920 ps
CPU time 15.67 seconds
Started Jul 07 05:31:31 PM PDT 24
Finished Jul 07 05:31:47 PM PDT 24
Peak memory 200360 kb
Host smart-f534f72d-8005-4212-8334-0852ccbb1cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262285102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3262285102
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3498127407
Short name T80
Test name
Test status
Simulation time 69803422410 ps
CPU time 429.84 seconds
Started Jul 07 05:31:38 PM PDT 24
Finished Jul 07 05:38:49 PM PDT 24
Peak memory 200392 kb
Host smart-2ef4321a-341b-4d70-81b2-5467c7788f5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498127407 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3498127407
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4001961166
Short name T204
Test name
Test status
Simulation time 9462314899 ps
CPU time 121.97 seconds
Started Jul 07 05:31:31 PM PDT 24
Finished Jul 07 05:33:34 PM PDT 24
Peak memory 200376 kb
Host smart-4b735572-0c9f-4cef-982a-ad068189e400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001961166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4001961166
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.864955360
Short name T173
Test name
Test status
Simulation time 79836818 ps
CPU time 0.59 seconds
Started Jul 07 05:31:39 PM PDT 24
Finished Jul 07 05:31:40 PM PDT 24
Peak memory 195148 kb
Host smart-fa74056a-c23d-487a-9d1c-5c995128f7e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864955360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.864955360
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3387295278
Short name T320
Test name
Test status
Simulation time 810127936 ps
CPU time 26.4 seconds
Started Jul 07 05:31:32 PM PDT 24
Finished Jul 07 05:31:59 PM PDT 24
Peak memory 200280 kb
Host smart-dbfc4e0c-07e8-433e-a38e-b8bbf74a3ce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387295278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3387295278
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1388764973
Short name T205
Test name
Test status
Simulation time 12211257002 ps
CPU time 44.63 seconds
Started Jul 07 05:31:36 PM PDT 24
Finished Jul 07 05:32:21 PM PDT 24
Peak memory 208584 kb
Host smart-9340721b-1364-40c3-a57a-239473e18387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388764973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1388764973
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3509506612
Short name T89
Test name
Test status
Simulation time 3591500197 ps
CPU time 25.39 seconds
Started Jul 07 05:31:35 PM PDT 24
Finished Jul 07 05:32:00 PM PDT 24
Peak memory 248656 kb
Host smart-b8d77827-4d44-408e-92b6-06f2c9e19fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509506612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3509506612
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.937036088
Short name T393
Test name
Test status
Simulation time 10954245426 ps
CPU time 195.84 seconds
Started Jul 07 05:31:34 PM PDT 24
Finished Jul 07 05:34:50 PM PDT 24
Peak memory 200384 kb
Host smart-4b5d36be-dd1f-4d17-98a0-8b5e3f755eeb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937036088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.937036088
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1855831478
Short name T336
Test name
Test status
Simulation time 4802852667 ps
CPU time 62.75 seconds
Started Jul 07 05:31:37 PM PDT 24
Finished Jul 07 05:32:40 PM PDT 24
Peak memory 200320 kb
Host smart-b0f286b5-4442-423c-95e6-0e017f8a66a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855831478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1855831478
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.207977060
Short name T370
Test name
Test status
Simulation time 2732388550 ps
CPU time 9 seconds
Started Jul 07 05:31:33 PM PDT 24
Finished Jul 07 05:31:42 PM PDT 24
Peak memory 200400 kb
Host smart-278c031d-914a-42d4-a406-895e5cb6e432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207977060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.207977060
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3641244386
Short name T304
Test name
Test status
Simulation time 122630702 ps
CPU time 2.89 seconds
Started Jul 07 05:31:33 PM PDT 24
Finished Jul 07 05:31:36 PM PDT 24
Peak memory 200280 kb
Host smart-382d65e0-d0eb-487b-882d-a17b332bd111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641244386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3641244386
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3019896807
Short name T47
Test name
Test status
Simulation time 12839850 ps
CPU time 0.62 seconds
Started Jul 07 05:31:38 PM PDT 24
Finished Jul 07 05:31:38 PM PDT 24
Peak memory 196192 kb
Host smart-0a48b6a9-8b9d-4653-a1e8-0cd380eaa915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019896807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3019896807
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.542590831
Short name T283
Test name
Test status
Simulation time 1016824329 ps
CPU time 23.98 seconds
Started Jul 07 05:31:42 PM PDT 24
Finished Jul 07 05:32:06 PM PDT 24
Peak memory 200276 kb
Host smart-e2727916-8a88-49f9-be11-7d8817d46dd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=542590831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.542590831
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3138586376
Short name T149
Test name
Test status
Simulation time 8359584928 ps
CPU time 43.9 seconds
Started Jul 07 05:31:36 PM PDT 24
Finished Jul 07 05:32:21 PM PDT 24
Peak memory 208560 kb
Host smart-d2de1029-5868-47ea-b28d-30d51ed471bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138586376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3138586376
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3545032332
Short name T517
Test name
Test status
Simulation time 12164441482 ps
CPU time 1058.15 seconds
Started Jul 07 05:31:35 PM PDT 24
Finished Jul 07 05:49:14 PM PDT 24
Peak memory 743524 kb
Host smart-7ab33bbe-0c81-4089-a70d-f727412591f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545032332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3545032332
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1920350509
Short name T452
Test name
Test status
Simulation time 7521343307 ps
CPU time 98.12 seconds
Started Jul 07 05:31:42 PM PDT 24
Finished Jul 07 05:33:21 PM PDT 24
Peak memory 200384 kb
Host smart-18915e4f-7f40-4dbc-88a0-e231cbb6fa4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920350509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1920350509
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.844552025
Short name T364
Test name
Test status
Simulation time 1967908741 ps
CPU time 107.26 seconds
Started Jul 07 05:31:38 PM PDT 24
Finished Jul 07 05:33:26 PM PDT 24
Peak memory 200320 kb
Host smart-fe2c3068-0197-4abc-9260-682d25429ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844552025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.844552025
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.4157962887
Short name T381
Test name
Test status
Simulation time 1023686406 ps
CPU time 9.69 seconds
Started Jul 07 05:31:37 PM PDT 24
Finished Jul 07 05:31:47 PM PDT 24
Peak memory 200272 kb
Host smart-d5eb73ff-6b76-4da3-95a8-da8c8a5d641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157962887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.4157962887
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.70605140
Short name T148
Test name
Test status
Simulation time 11263578974 ps
CPU time 558.39 seconds
Started Jul 07 05:31:43 PM PDT 24
Finished Jul 07 05:41:01 PM PDT 24
Peak memory 200368 kb
Host smart-77686a91-ad4b-4f1c-b047-3d54bb3d22c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70605140 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.70605140
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.612216974
Short name T351
Test name
Test status
Simulation time 46735794221 ps
CPU time 147.58 seconds
Started Jul 07 05:31:43 PM PDT 24
Finished Jul 07 05:34:11 PM PDT 24
Peak memory 200404 kb
Host smart-a2038e11-307d-4fef-9e0c-1675b710705d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612216974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.612216974
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3438560228
Short name T59
Test name
Test status
Simulation time 13657762 ps
CPU time 0.59 seconds
Started Jul 07 05:31:40 PM PDT 24
Finished Jul 07 05:31:41 PM PDT 24
Peak memory 195152 kb
Host smart-42bc4feb-16c7-415e-becb-6f6925719964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438560228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3438560228
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1701531812
Short name T423
Test name
Test status
Simulation time 75583610 ps
CPU time 2.05 seconds
Started Jul 07 05:31:37 PM PDT 24
Finished Jul 07 05:31:40 PM PDT 24
Peak memory 200248 kb
Host smart-c08d2b5f-203e-4822-b27e-20b148928b4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701531812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1701531812
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.4244913559
Short name T123
Test name
Test status
Simulation time 2116440255 ps
CPU time 28.82 seconds
Started Jul 07 05:31:38 PM PDT 24
Finished Jul 07 05:32:07 PM PDT 24
Peak memory 200292 kb
Host smart-5b1ca33c-98a8-434b-baef-f3f32fccb0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244913559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.4244913559
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.551761624
Short name T231
Test name
Test status
Simulation time 948327631 ps
CPU time 112.89 seconds
Started Jul 07 05:31:39 PM PDT 24
Finished Jul 07 05:33:32 PM PDT 24
Peak memory 329052 kb
Host smart-f82ef9a1-126f-4b1a-bdf5-e5d08ae53cf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551761624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.551761624
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2681602965
Short name T391
Test name
Test status
Simulation time 26415912313 ps
CPU time 127.61 seconds
Started Jul 07 05:31:40 PM PDT 24
Finished Jul 07 05:33:48 PM PDT 24
Peak memory 216800 kb
Host smart-c2bbea80-3f18-4902-a12a-234e402098f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681602965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2681602965
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2911195908
Short name T375
Test name
Test status
Simulation time 1328718433 ps
CPU time 4.99 seconds
Started Jul 07 05:31:39 PM PDT 24
Finished Jul 07 05:31:44 PM PDT 24
Peak memory 200236 kb
Host smart-b2f11f3f-4c38-42d0-a93b-2e190e56894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911195908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2911195908
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2535828852
Short name T518
Test name
Test status
Simulation time 89576878253 ps
CPU time 1792.92 seconds
Started Jul 07 05:31:37 PM PDT 24
Finished Jul 07 06:01:30 PM PDT 24
Peak memory 679248 kb
Host smart-e54d9dbd-3a0b-4596-ac53-fd8df391b574
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535828852 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2535828852
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.697388192
Short name T269
Test name
Test status
Simulation time 10266002311 ps
CPU time 66.74 seconds
Started Jul 07 05:31:41 PM PDT 24
Finished Jul 07 05:32:48 PM PDT 24
Peak memory 200332 kb
Host smart-bc00bee8-b7b4-4fa3-838e-f16b65d56a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697388192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.697388192
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2041483174
Short name T298
Test name
Test status
Simulation time 90034018 ps
CPU time 0.59 seconds
Started Jul 07 05:31:52 PM PDT 24
Finished Jul 07 05:31:54 PM PDT 24
Peak memory 196196 kb
Host smart-1fa6a797-fbf3-4dc1-a21f-ac1d0fea4235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041483174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2041483174
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.51207421
Short name T236
Test name
Test status
Simulation time 265663255 ps
CPU time 15.97 seconds
Started Jul 07 05:31:45 PM PDT 24
Finished Jul 07 05:32:02 PM PDT 24
Peak memory 200324 kb
Host smart-8e0ef3c9-689c-4c65-bfb2-33b9c5b70292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51207421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.51207421
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.69874789
Short name T302
Test name
Test status
Simulation time 2099853081 ps
CPU time 27.93 seconds
Started Jul 07 05:31:40 PM PDT 24
Finished Jul 07 05:32:08 PM PDT 24
Peak memory 200312 kb
Host smart-e11a05c4-41a7-4a94-8934-9cd2409d9020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69874789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.69874789
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3127831632
Short name T266
Test name
Test status
Simulation time 6593818028 ps
CPU time 588.96 seconds
Started Jul 07 05:31:43 PM PDT 24
Finished Jul 07 05:41:32 PM PDT 24
Peak memory 644636 kb
Host smart-536f7f2d-625e-4354-9fe2-3bf615d9b919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3127831632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3127831632
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.412763494
Short name T150
Test name
Test status
Simulation time 10521914036 ps
CPU time 48.66 seconds
Started Jul 07 05:31:44 PM PDT 24
Finished Jul 07 05:32:33 PM PDT 24
Peak memory 200276 kb
Host smart-2ad254a7-318d-4d34-aa89-dca2a7e569ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412763494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.412763494
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3354591597
Short name T476
Test name
Test status
Simulation time 405829492 ps
CPU time 22.67 seconds
Started Jul 07 05:31:37 PM PDT 24
Finished Jul 07 05:32:00 PM PDT 24
Peak memory 200308 kb
Host smart-7bb3f88a-e8e0-4fc6-8266-cf38ee0fe274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354591597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3354591597
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1381137586
Short name T133
Test name
Test status
Simulation time 151743216 ps
CPU time 4.46 seconds
Started Jul 07 05:31:33 PM PDT 24
Finished Jul 07 05:31:38 PM PDT 24
Peak memory 200260 kb
Host smart-da950a03-6608-43d8-95d2-04f23ec8650d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381137586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1381137586
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4030799028
Short name T338
Test name
Test status
Simulation time 22127248735 ps
CPU time 2167.62 seconds
Started Jul 07 05:31:45 PM PDT 24
Finished Jul 07 06:07:53 PM PDT 24
Peak memory 792232 kb
Host smart-ab4a586c-3a93-4410-9e54-75a96280eb36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030799028 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4030799028
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3692109106
Short name T233
Test name
Test status
Simulation time 638367530 ps
CPU time 33.17 seconds
Started Jul 07 05:31:42 PM PDT 24
Finished Jul 07 05:32:16 PM PDT 24
Peak memory 200372 kb
Host smart-5d1f4d0a-fe36-4e21-9ea0-366d357ec713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692109106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3692109106
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3449811438
Short name T296
Test name
Test status
Simulation time 35718135 ps
CPU time 0.59 seconds
Started Jul 07 05:31:53 PM PDT 24
Finished Jul 07 05:31:54 PM PDT 24
Peak memory 195828 kb
Host smart-d4cf75f9-b3da-43f7-99bc-113c6dcec322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449811438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3449811438
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.120428660
Short name T379
Test name
Test status
Simulation time 282097785 ps
CPU time 1.98 seconds
Started Jul 07 05:31:45 PM PDT 24
Finished Jul 07 05:31:48 PM PDT 24
Peak memory 200280 kb
Host smart-6e600158-e323-471b-83eb-c17681a9ba38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=120428660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.120428660
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.981439160
Short name T434
Test name
Test status
Simulation time 2010656067 ps
CPU time 27.41 seconds
Started Jul 07 05:31:52 PM PDT 24
Finished Jul 07 05:32:20 PM PDT 24
Peak memory 200344 kb
Host smart-a89f15ec-6317-4f50-8873-6ce71a6e85ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981439160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.981439160
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.838270458
Short name T337
Test name
Test status
Simulation time 20917351381 ps
CPU time 817.93 seconds
Started Jul 07 05:31:39 PM PDT 24
Finished Jul 07 05:45:17 PM PDT 24
Peak memory 724676 kb
Host smart-ad15c734-601d-4b22-b59c-22b64a4ab6c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=838270458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.838270458
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.972764434
Short name T263
Test name
Test status
Simulation time 4068670109 ps
CPU time 109.4 seconds
Started Jul 07 05:31:52 PM PDT 24
Finished Jul 07 05:33:43 PM PDT 24
Peak memory 200340 kb
Host smart-f549cc0f-353d-41b2-9cbf-625e582f6dbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972764434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.972764434
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2942446434
Short name T415
Test name
Test status
Simulation time 725911683 ps
CPU time 10.13 seconds
Started Jul 07 05:31:43 PM PDT 24
Finished Jul 07 05:31:53 PM PDT 24
Peak memory 200340 kb
Host smart-a267ffba-3804-4f1b-b9c8-4acb059a54b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942446434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2942446434
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2552262679
Short name T262
Test name
Test status
Simulation time 113724899 ps
CPU time 5.05 seconds
Started Jul 07 05:31:42 PM PDT 24
Finished Jul 07 05:31:47 PM PDT 24
Peak memory 200344 kb
Host smart-e0fccc61-b617-4b5e-ab4b-c2fae76a6858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552262679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2552262679
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1650789810
Short name T314
Test name
Test status
Simulation time 385188514137 ps
CPU time 2747.22 seconds
Started Jul 07 05:31:44 PM PDT 24
Finished Jul 07 06:17:32 PM PDT 24
Peak memory 783128 kb
Host smart-abcbd22b-10ec-41df-8efe-17ea8c276a06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650789810 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1650789810
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.229320919
Short name T411
Test name
Test status
Simulation time 3160960161 ps
CPU time 70.74 seconds
Started Jul 07 05:31:52 PM PDT 24
Finished Jul 07 05:33:03 PM PDT 24
Peak memory 200356 kb
Host smart-3a22c140-11e9-4b73-a646-fee8723fc08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229320919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.229320919
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2123439144
Short name T398
Test name
Test status
Simulation time 20224981 ps
CPU time 0.58 seconds
Started Jul 07 05:31:44 PM PDT 24
Finished Jul 07 05:31:45 PM PDT 24
Peak memory 195672 kb
Host smart-ea8b4720-69e5-4bd0-9e35-3e163b77b1a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123439144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2123439144
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2092923970
Short name T507
Test name
Test status
Simulation time 1460631509 ps
CPU time 77.59 seconds
Started Jul 07 05:31:41 PM PDT 24
Finished Jul 07 05:32:58 PM PDT 24
Peak memory 200260 kb
Host smart-756acac7-1823-4253-a027-bc7b52b33ff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092923970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2092923970
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.200873579
Short name T6
Test name
Test status
Simulation time 2033938748 ps
CPU time 39.71 seconds
Started Jul 07 05:31:46 PM PDT 24
Finished Jul 07 05:32:26 PM PDT 24
Peak memory 200256 kb
Host smart-d3f889c7-1459-4e1a-b37b-b0dcdbad4538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200873579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.200873579
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3852242431
Short name T166
Test name
Test status
Simulation time 311860222 ps
CPU time 48.72 seconds
Started Jul 07 05:31:40 PM PDT 24
Finished Jul 07 05:32:29 PM PDT 24
Peak memory 324284 kb
Host smart-a1d42b8f-26b2-416a-9832-e0e2baaf77bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852242431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3852242431
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.995934123
Short name T520
Test name
Test status
Simulation time 1023289659 ps
CPU time 57.56 seconds
Started Jul 07 05:31:51 PM PDT 24
Finished Jul 07 05:32:50 PM PDT 24
Peak memory 200088 kb
Host smart-fd77ebd4-297b-4a36-8aff-56edd038f97f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995934123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.995934123
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3132760430
Short name T465
Test name
Test status
Simulation time 851671260 ps
CPU time 49.05 seconds
Started Jul 07 05:31:40 PM PDT 24
Finished Jul 07 05:32:29 PM PDT 24
Peak memory 200332 kb
Host smart-2b044333-697f-44cf-b009-75baf07b47e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132760430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3132760430
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.4106993270
Short name T178
Test name
Test status
Simulation time 2627943358 ps
CPU time 15.69 seconds
Started Jul 07 05:31:51 PM PDT 24
Finished Jul 07 05:32:07 PM PDT 24
Peak memory 200336 kb
Host smart-2ec1ec00-bbba-419b-a1e3-75fceec824e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106993270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.4106993270
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3821660318
Short name T49
Test name
Test status
Simulation time 19419998150 ps
CPU time 316.86 seconds
Started Jul 07 05:31:42 PM PDT 24
Finished Jul 07 05:36:59 PM PDT 24
Peak memory 216644 kb
Host smart-7a637186-e188-462b-a4d3-4bf6c6ad7731
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821660318 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3821660318
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.447631019
Short name T8
Test name
Test status
Simulation time 1686681702 ps
CPU time 27.05 seconds
Started Jul 07 05:31:51 PM PDT 24
Finished Jul 07 05:32:19 PM PDT 24
Peak memory 200224 kb
Host smart-5af7054f-19e8-48ab-ae5d-d23382054511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447631019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.447631019
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1144335964
Short name T176
Test name
Test status
Simulation time 13370243 ps
CPU time 0.58 seconds
Started Jul 07 05:31:12 PM PDT 24
Finished Jul 07 05:31:13 PM PDT 24
Peak memory 196872 kb
Host smart-9ed6fb91-7fb6-4361-a6af-12bb1f339ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144335964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1144335964
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.943682279
Short name T308
Test name
Test status
Simulation time 1202487169 ps
CPU time 34.12 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:31:41 PM PDT 24
Peak memory 200280 kb
Host smart-e853d02b-6a0b-4ffe-ab7d-90a4ac5aba66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943682279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.943682279
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.793677883
Short name T378
Test name
Test status
Simulation time 15668507523 ps
CPU time 61.39 seconds
Started Jul 07 05:30:54 PM PDT 24
Finished Jul 07 05:31:56 PM PDT 24
Peak memory 200328 kb
Host smart-bdaf5712-a2e0-4915-9056-52084c1ec470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793677883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.793677883
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3819356508
Short name T512
Test name
Test status
Simulation time 321042310 ps
CPU time 6.09 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:08 PM PDT 24
Peak memory 200292 kb
Host smart-a1f9aeec-f4ff-49d1-9a2c-ae772f96b1e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819356508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3819356508
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.94490197
Short name T153
Test name
Test status
Simulation time 41327824 ps
CPU time 0.83 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:31:05 PM PDT 24
Peak memory 198132 kb
Host smart-9962f83d-2470-4d71-a601-150e615ffb0a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94490197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.94490197
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2303794021
Short name T341
Test name
Test status
Simulation time 10143576858 ps
CPU time 181.51 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:33:52 PM PDT 24
Peak memory 200456 kb
Host smart-734faffd-1c85-4d37-a14f-fa1aa396cf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303794021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2303794021
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3252655672
Short name T65
Test name
Test status
Simulation time 123424820 ps
CPU time 0.81 seconds
Started Jul 07 05:30:59 PM PDT 24
Finished Jul 07 05:31:00 PM PDT 24
Peak memory 218360 kb
Host smart-624afc39-246b-46dc-bb97-682adb9bff19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252655672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3252655672
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1473119576
Short name T354
Test name
Test status
Simulation time 255037317 ps
CPU time 3.73 seconds
Started Jul 07 05:30:53 PM PDT 24
Finished Jul 07 05:30:57 PM PDT 24
Peak memory 200308 kb
Host smart-da3c8edd-930b-417d-a413-f6fda7bc8cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473119576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1473119576
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1717641840
Short name T483
Test name
Test status
Simulation time 23544820489 ps
CPU time 323.3 seconds
Started Jul 07 05:30:52 PM PDT 24
Finished Jul 07 05:36:16 PM PDT 24
Peak memory 216700 kb
Host smart-3d2b9f80-6670-4baa-abb2-206bbcfc305e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717641840 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1717641840
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2155375881
Short name T77
Test name
Test status
Simulation time 21729911444 ps
CPU time 247.23 seconds
Started Jul 07 05:30:54 PM PDT 24
Finished Jul 07 05:35:01 PM PDT 24
Peak memory 209716 kb
Host smart-a65b3faf-7662-40e9-baa8-22e2317d800c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155375881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2155375881
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2385811801
Short name T267
Test name
Test status
Simulation time 15060793352 ps
CPU time 74.02 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:32:04 PM PDT 24
Peak memory 200328 kb
Host smart-acbda637-352d-4a18-b7b2-2fd2d9f14448
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2385811801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2385811801
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2063579944
Short name T309
Test name
Test status
Simulation time 21733674381 ps
CPU time 61.37 seconds
Started Jul 07 05:30:54 PM PDT 24
Finished Jul 07 05:31:56 PM PDT 24
Peak memory 200208 kb
Host smart-461a5fbe-2af9-4246-8edb-8b8c62b4d37f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2063579944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2063579944
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2795880630
Short name T301
Test name
Test status
Simulation time 11404094680 ps
CPU time 113.04 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:32:49 PM PDT 24
Peak memory 200208 kb
Host smart-3fffb948-5e36-49ac-97e1-e00e18de86fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2795880630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2795880630
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.4224244826
Short name T498
Test name
Test status
Simulation time 167646099789 ps
CPU time 613.95 seconds
Started Jul 07 05:30:58 PM PDT 24
Finished Jul 07 05:41:12 PM PDT 24
Peak memory 200384 kb
Host smart-017eb062-d9e2-4f4f-831a-239e9182256c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4224244826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.4224244826
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.933647008
Short name T3
Test name
Test status
Simulation time 157310447448 ps
CPU time 2341.01 seconds
Started Jul 07 05:30:56 PM PDT 24
Finished Jul 07 06:09:58 PM PDT 24
Peak memory 215740 kb
Host smart-9a775218-774f-42dd-8564-672700ae9fd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=933647008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.933647008
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3664093634
Short name T138
Test name
Test status
Simulation time 316952643720 ps
CPU time 2593.14 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 06:14:09 PM PDT 24
Peak memory 215816 kb
Host smart-f6d286b1-4cd7-4913-8955-bf6554b1114f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3664093634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3664093634
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2114483290
Short name T401
Test name
Test status
Simulation time 15101793585 ps
CPU time 93.27 seconds
Started Jul 07 05:30:57 PM PDT 24
Finished Jul 07 05:32:30 PM PDT 24
Peak memory 200344 kb
Host smart-25586c54-abb0-4312-bef8-0418fd245ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114483290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2114483290
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1155372192
Short name T286
Test name
Test status
Simulation time 21801014 ps
CPU time 0.58 seconds
Started Jul 07 05:31:46 PM PDT 24
Finished Jul 07 05:31:47 PM PDT 24
Peak memory 195116 kb
Host smart-66a5a55f-2170-42a1-86ba-17a09bccb8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155372192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1155372192
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1617553201
Short name T192
Test name
Test status
Simulation time 1658611135 ps
CPU time 44.23 seconds
Started Jul 07 05:31:46 PM PDT 24
Finished Jul 07 05:32:30 PM PDT 24
Peak memory 200276 kb
Host smart-eab123ab-3a75-4552-ad98-35d9567218a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617553201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1617553201
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.792870110
Short name T294
Test name
Test status
Simulation time 48745945245 ps
CPU time 53.77 seconds
Started Jul 07 05:31:47 PM PDT 24
Finished Jul 07 05:32:41 PM PDT 24
Peak memory 200360 kb
Host smart-4e9322ea-7d11-4c76-be1d-eafae9152f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792870110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.792870110
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.814454655
Short name T181
Test name
Test status
Simulation time 3032931429 ps
CPU time 501.05 seconds
Started Jul 07 05:31:42 PM PDT 24
Finished Jul 07 05:40:03 PM PDT 24
Peak memory 662192 kb
Host smart-52a8c8a4-4dc7-4b5a-9e4b-2d496c2102e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814454655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.814454655
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.150600399
Short name T496
Test name
Test status
Simulation time 65806215867 ps
CPU time 270.28 seconds
Started Jul 07 05:31:52 PM PDT 24
Finished Jul 07 05:36:24 PM PDT 24
Peak memory 200340 kb
Host smart-31e288a1-f924-41c2-96c6-8cb669c08796
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150600399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.150600399
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3309869604
Short name T519
Test name
Test status
Simulation time 1638577385 ps
CPU time 86.42 seconds
Started Jul 07 05:31:45 PM PDT 24
Finished Jul 07 05:33:12 PM PDT 24
Peak memory 200248 kb
Host smart-92fba145-e1c9-4e7b-8dcb-4f1f2ae476fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309869604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3309869604
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.15818484
Short name T471
Test name
Test status
Simulation time 1114243066 ps
CPU time 13.17 seconds
Started Jul 07 05:31:45 PM PDT 24
Finished Jul 07 05:31:59 PM PDT 24
Peak memory 200324 kb
Host smart-8fb5c4b1-f67b-4fcf-a5e4-9ba0a438f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15818484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.15818484
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.188375636
Short name T147
Test name
Test status
Simulation time 129367668799 ps
CPU time 3851.66 seconds
Started Jul 07 05:31:42 PM PDT 24
Finished Jul 07 06:35:55 PM PDT 24
Peak memory 866096 kb
Host smart-31117e67-5fb0-48bc-a9d6-0b7cd214aaea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188375636 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.188375636
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3625795325
Short name T94
Test name
Test status
Simulation time 2003490238 ps
CPU time 30.67 seconds
Started Jul 07 05:31:41 PM PDT 24
Finished Jul 07 05:32:12 PM PDT 24
Peak memory 200300 kb
Host smart-8c811606-126e-4f09-99ca-ed1f8be62d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625795325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3625795325
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3606280029
Short name T245
Test name
Test status
Simulation time 29784394 ps
CPU time 0.59 seconds
Started Jul 07 05:31:44 PM PDT 24
Finished Jul 07 05:31:44 PM PDT 24
Peak memory 196868 kb
Host smart-a8beaa0a-cbf5-486a-9611-88f4a7ca3fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606280029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3606280029
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4194451455
Short name T328
Test name
Test status
Simulation time 1433477726 ps
CPU time 89.48 seconds
Started Jul 07 05:31:47 PM PDT 24
Finished Jul 07 05:33:17 PM PDT 24
Peak memory 200280 kb
Host smart-34122c84-b09b-45d1-b4be-41ad70d42be9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194451455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4194451455
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.227134749
Short name T396
Test name
Test status
Simulation time 1167642096 ps
CPU time 20.46 seconds
Started Jul 07 05:31:51 PM PDT 24
Finished Jul 07 05:32:12 PM PDT 24
Peak memory 200344 kb
Host smart-9b83ff8f-8f69-4a9f-98a6-c2322d9f419d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227134749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.227134749
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2925372948
Short name T42
Test name
Test status
Simulation time 321793385 ps
CPU time 33.1 seconds
Started Jul 07 05:31:46 PM PDT 24
Finished Jul 07 05:32:19 PM PDT 24
Peak memory 246944 kb
Host smart-3cf300ec-ae34-473a-808b-8db0c6cd190e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925372948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2925372948
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1713833822
Short name T291
Test name
Test status
Simulation time 59802870005 ps
CPU time 137.02 seconds
Started Jul 07 05:31:44 PM PDT 24
Finished Jul 07 05:34:01 PM PDT 24
Peak memory 200340 kb
Host smart-a10f0a82-4b4e-41e9-931d-cbfa5a5cd6fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713833822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1713833822
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1654464752
Short name T1
Test name
Test status
Simulation time 4342204101 ps
CPU time 28.91 seconds
Started Jul 07 05:31:45 PM PDT 24
Finished Jul 07 05:32:14 PM PDT 24
Peak memory 200360 kb
Host smart-a6a7b9ca-aa45-4b44-9efe-7d8ed0f0157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654464752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1654464752
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.659384281
Short name T347
Test name
Test status
Simulation time 1059202869 ps
CPU time 12.53 seconds
Started Jul 07 05:31:43 PM PDT 24
Finished Jul 07 05:31:56 PM PDT 24
Peak memory 200312 kb
Host smart-534d1de2-3dce-4844-9f1a-1d2a2b3913e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659384281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.659384281
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1719271785
Short name T413
Test name
Test status
Simulation time 53786934393 ps
CPU time 1682.93 seconds
Started Jul 07 05:31:51 PM PDT 24
Finished Jul 07 05:59:55 PM PDT 24
Peak memory 508752 kb
Host smart-4bbfc386-faaa-4dfb-a4b4-6f133bf42645
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719271785 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1719271785
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3563572038
Short name T422
Test name
Test status
Simulation time 7085059066 ps
CPU time 130.33 seconds
Started Jul 07 05:31:43 PM PDT 24
Finished Jul 07 05:33:54 PM PDT 24
Peak memory 200416 kb
Host smart-d092e3dc-d904-4b8c-9360-9ba28508673b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563572038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3563572038
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3964079047
Short name T499
Test name
Test status
Simulation time 11095527 ps
CPU time 0.56 seconds
Started Jul 07 05:31:51 PM PDT 24
Finished Jul 07 05:31:52 PM PDT 24
Peak memory 195128 kb
Host smart-0491eaea-01ad-4f34-9643-981546668ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964079047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3964079047
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3130181141
Short name T137
Test name
Test status
Simulation time 1662780806 ps
CPU time 92.27 seconds
Started Jul 07 05:31:54 PM PDT 24
Finished Jul 07 05:33:27 PM PDT 24
Peak memory 200328 kb
Host smart-0fd52150-632e-4cf1-9437-bb38be767c17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3130181141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3130181141
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2309828658
Short name T334
Test name
Test status
Simulation time 1948866653 ps
CPU time 43.53 seconds
Started Jul 07 05:31:50 PM PDT 24
Finished Jul 07 05:32:34 PM PDT 24
Peak memory 200296 kb
Host smart-e5d3a6c5-31f3-47da-82c2-92fe98b65b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309828658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2309828658
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.701432357
Short name T369
Test name
Test status
Simulation time 6492563648 ps
CPU time 587.61 seconds
Started Jul 07 05:31:48 PM PDT 24
Finished Jul 07 05:41:36 PM PDT 24
Peak memory 489384 kb
Host smart-8ef344db-1104-4360-b4d8-4a67cc8ec74b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=701432357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.701432357
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.637487370
Short name T280
Test name
Test status
Simulation time 48864983256 ps
CPU time 147.63 seconds
Started Jul 07 05:31:49 PM PDT 24
Finished Jul 07 05:34:17 PM PDT 24
Peak memory 200312 kb
Host smart-1bec9114-1eec-4058-8907-8f1f0afcf16f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637487370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.637487370
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4274118790
Short name T136
Test name
Test status
Simulation time 10679501079 ps
CPU time 89.61 seconds
Started Jul 07 05:31:51 PM PDT 24
Finished Jul 07 05:33:21 PM PDT 24
Peak memory 200340 kb
Host smart-819af0ad-0c96-472d-8334-729a610b34cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274118790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4274118790
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1009035995
Short name T282
Test name
Test status
Simulation time 1249165971 ps
CPU time 16.09 seconds
Started Jul 07 05:31:46 PM PDT 24
Finished Jul 07 05:32:02 PM PDT 24
Peak memory 200308 kb
Host smart-6066d44b-dbfc-4ea4-bc9a-ba98c3fb21a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009035995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1009035995
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2135907942
Short name T480
Test name
Test status
Simulation time 819183821086 ps
CPU time 2799.96 seconds
Started Jul 07 05:31:54 PM PDT 24
Finished Jul 07 06:18:35 PM PDT 24
Peak memory 813016 kb
Host smart-06f7511a-e8b4-4b11-84ce-fa6256bc34ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135907942 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2135907942
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1674842433
Short name T243
Test name
Test status
Simulation time 898156547 ps
CPU time 44.2 seconds
Started Jul 07 05:31:48 PM PDT 24
Finished Jul 07 05:32:32 PM PDT 24
Peak memory 200300 kb
Host smart-2b7ec37b-de0a-4620-842b-0a904c7ec012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674842433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1674842433
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.872854391
Short name T497
Test name
Test status
Simulation time 10375414 ps
CPU time 0.57 seconds
Started Jul 07 05:31:55 PM PDT 24
Finished Jul 07 05:31:56 PM PDT 24
Peak memory 195804 kb
Host smart-49783b9f-8cca-42b6-a940-7d33f1892f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872854391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.872854391
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.311582857
Short name T493
Test name
Test status
Simulation time 516726760 ps
CPU time 29.36 seconds
Started Jul 07 05:31:53 PM PDT 24
Finished Jul 07 05:32:23 PM PDT 24
Peak memory 200148 kb
Host smart-d0d9d390-06dd-4d07-a583-fe385e14c13c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311582857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.311582857
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.766441602
Short name T436
Test name
Test status
Simulation time 25575267036 ps
CPU time 96.75 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:33:35 PM PDT 24
Peak memory 208568 kb
Host smart-efdfbcf9-db6d-4484-863e-ffde7f358d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766441602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.766441602
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.570258304
Short name T380
Test name
Test status
Simulation time 5031970600 ps
CPU time 237.45 seconds
Started Jul 07 05:31:51 PM PDT 24
Finished Jul 07 05:35:48 PM PDT 24
Peak memory 490604 kb
Host smart-c19fad5e-70d6-421c-a517-1d53652c2aaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570258304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.570258304
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3038306469
Short name T57
Test name
Test status
Simulation time 13984841833 ps
CPU time 207.75 seconds
Started Jul 07 05:31:52 PM PDT 24
Finished Jul 07 05:35:20 PM PDT 24
Peak memory 200388 kb
Host smart-ec4711fe-afe6-4192-8d99-f3bb049d8277
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038306469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3038306469
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1196774006
Short name T40
Test name
Test status
Simulation time 11754643979 ps
CPU time 106.3 seconds
Started Jul 07 05:31:54 PM PDT 24
Finished Jul 07 05:33:40 PM PDT 24
Peak memory 200364 kb
Host smart-eb8ab261-5e78-45a0-9cab-fb5112f5ca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196774006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1196774006
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.155553274
Short name T140
Test name
Test status
Simulation time 1122165010 ps
CPU time 14.07 seconds
Started Jul 07 05:31:49 PM PDT 24
Finished Jul 07 05:32:03 PM PDT 24
Peak memory 200608 kb
Host smart-71df35bb-9e40-405b-81e9-eee21f738f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155553274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.155553274
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.192322498
Short name T360
Test name
Test status
Simulation time 75603523295 ps
CPU time 2176.77 seconds
Started Jul 07 05:31:51 PM PDT 24
Finished Jul 07 06:08:08 PM PDT 24
Peak memory 776548 kb
Host smart-b9f4f170-73d5-4b0e-841b-07a20f781194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192322498 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.192322498
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2025293506
Short name T358
Test name
Test status
Simulation time 4000293401 ps
CPU time 103.66 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:33:42 PM PDT 24
Peak memory 200360 kb
Host smart-803c6ba6-d7bb-46d9-b25d-d08b66136f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025293506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2025293506
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1795857932
Short name T53
Test name
Test status
Simulation time 16088015 ps
CPU time 0.64 seconds
Started Jul 07 05:31:51 PM PDT 24
Finished Jul 07 05:31:53 PM PDT 24
Peak memory 196192 kb
Host smart-e5a38c52-4cd0-43c5-95c9-ec585c242f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795857932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1795857932
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1417436711
Short name T491
Test name
Test status
Simulation time 924442806 ps
CPU time 12.6 seconds
Started Jul 07 05:31:54 PM PDT 24
Finished Jul 07 05:32:07 PM PDT 24
Peak memory 200184 kb
Host smart-50caa984-ac2f-4731-b1db-adc269824f1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417436711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1417436711
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2800220037
Short name T371
Test name
Test status
Simulation time 3454953774 ps
CPU time 55.37 seconds
Started Jul 07 05:31:52 PM PDT 24
Finished Jul 07 05:32:48 PM PDT 24
Peak memory 200404 kb
Host smart-bcfec8cb-925e-408d-b4b6-566d0d2cbf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800220037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2800220037
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1473522306
Short name T37
Test name
Test status
Simulation time 8209493557 ps
CPU time 280.64 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:36:39 PM PDT 24
Peak memory 475920 kb
Host smart-064b2cc7-66e1-4329-9abc-a2de2ef112d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1473522306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1473522306
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.173662331
Short name T515
Test name
Test status
Simulation time 83237514553 ps
CPU time 144.28 seconds
Started Jul 07 05:31:53 PM PDT 24
Finished Jul 07 05:34:18 PM PDT 24
Peak memory 200384 kb
Host smart-11f85f70-229a-4463-b01c-9c7035580e1c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173662331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.173662331
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4178127835
Short name T217
Test name
Test status
Simulation time 9044651762 ps
CPU time 161.2 seconds
Started Jul 07 05:31:56 PM PDT 24
Finished Jul 07 05:34:37 PM PDT 24
Peak memory 200408 kb
Host smart-b91a82b3-fdd2-403b-b0e2-dc7b0739267a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178127835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4178127835
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3660652952
Short name T330
Test name
Test status
Simulation time 283469341 ps
CPU time 13.79 seconds
Started Jul 07 05:31:54 PM PDT 24
Finished Jul 07 05:32:08 PM PDT 24
Peak memory 200312 kb
Host smart-0d3d8cab-2455-4247-bfdb-c594deca9399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660652952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3660652952
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1405376588
Short name T67
Test name
Test status
Simulation time 23921949478 ps
CPU time 1107.41 seconds
Started Jul 07 05:31:53 PM PDT 24
Finished Jul 07 05:50:21 PM PDT 24
Peak memory 725724 kb
Host smart-27c24d1b-fd0f-4121-b3f7-7f7dd960083f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405376588 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1405376588
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.359404199
Short name T414
Test name
Test status
Simulation time 19269462375 ps
CPU time 86.54 seconds
Started Jul 07 05:31:52 PM PDT 24
Finished Jul 07 05:33:19 PM PDT 24
Peak memory 200368 kb
Host smart-1704163b-672e-4e36-bb2e-cb49c26e7fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359404199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.359404199
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.666546016
Short name T425
Test name
Test status
Simulation time 11406807 ps
CPU time 0.57 seconds
Started Jul 07 05:31:56 PM PDT 24
Finished Jul 07 05:31:57 PM PDT 24
Peak memory 195168 kb
Host smart-acb24dca-30da-4952-9902-986fd0e495d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666546016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.666546016
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3691678871
Short name T234
Test name
Test status
Simulation time 4456996365 ps
CPU time 64.94 seconds
Started Jul 07 05:31:53 PM PDT 24
Finished Jul 07 05:32:58 PM PDT 24
Peak memory 200300 kb
Host smart-92bcc4f0-07a7-4f12-93f2-c1c50e826821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691678871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3691678871
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1926771841
Short name T10
Test name
Test status
Simulation time 2707239035 ps
CPU time 40.09 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:32:38 PM PDT 24
Peak memory 200364 kb
Host smart-fad9b94c-087d-476c-8d99-2836ddefeb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926771841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1926771841
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2811351332
Short name T463
Test name
Test status
Simulation time 4122773541 ps
CPU time 704.09 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:43:43 PM PDT 24
Peak memory 655132 kb
Host smart-e02d2c90-7e06-4eda-acfb-5e4e54de95a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811351332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2811351332
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4076998474
Short name T525
Test name
Test status
Simulation time 12615571872 ps
CPU time 219.46 seconds
Started Jul 07 05:31:56 PM PDT 24
Finished Jul 07 05:35:36 PM PDT 24
Peak memory 200616 kb
Host smart-59dcb3a0-62c6-4354-9301-5e2bb4b886d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076998474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4076998474
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1289851192
Short name T151
Test name
Test status
Simulation time 2883123576 ps
CPU time 85.09 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:33:24 PM PDT 24
Peak memory 200356 kb
Host smart-31a85514-b614-4ffc-9001-41afe736634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289851192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1289851192
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.600460156
Short name T399
Test name
Test status
Simulation time 583439492 ps
CPU time 7.82 seconds
Started Jul 07 05:31:55 PM PDT 24
Finished Jul 07 05:32:04 PM PDT 24
Peak memory 200308 kb
Host smart-5ecf34ca-8252-4065-9be3-39135c0d4a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600460156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.600460156
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.4259048316
Short name T189
Test name
Test status
Simulation time 5045635193 ps
CPU time 59.35 seconds
Started Jul 07 05:31:55 PM PDT 24
Finished Jul 07 05:32:55 PM PDT 24
Peak memory 200344 kb
Host smart-9e800772-d640-4dee-b099-171845895966
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259048316 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.4259048316
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4106355169
Short name T98
Test name
Test status
Simulation time 95241513335 ps
CPU time 62.37 seconds
Started Jul 07 05:31:59 PM PDT 24
Finished Jul 07 05:33:02 PM PDT 24
Peak memory 200312 kb
Host smart-006e65c0-ec2c-43a6-a82f-ae107ca995d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106355169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4106355169
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.397922468
Short name T255
Test name
Test status
Simulation time 35958816 ps
CPU time 0.62 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:31:59 PM PDT 24
Peak memory 196184 kb
Host smart-f04873c2-09dc-474c-96b8-e0c702e459c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397922468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.397922468
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.246459170
Short name T418
Test name
Test status
Simulation time 2971691621 ps
CPU time 44.61 seconds
Started Jul 07 05:31:56 PM PDT 24
Finished Jul 07 05:32:41 PM PDT 24
Peak memory 200376 kb
Host smart-50e65ded-9b02-490d-bb02-d2b7fc03817f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246459170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.246459170
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1697929520
Short name T409
Test name
Test status
Simulation time 286950507 ps
CPU time 0.84 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:32:00 PM PDT 24
Peak memory 199056 kb
Host smart-6dee972f-2d09-4fa7-8ab6-99c54f3e37af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697929520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1697929520
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3886064564
Short name T430
Test name
Test status
Simulation time 1540576877 ps
CPU time 179.79 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:34:59 PM PDT 24
Peak memory 341300 kb
Host smart-294ba654-b9a3-4afd-b804-329043e4bd53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886064564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3886064564
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.912616751
Short name T92
Test name
Test status
Simulation time 9475242820 ps
CPU time 123.8 seconds
Started Jul 07 05:31:55 PM PDT 24
Finished Jul 07 05:34:00 PM PDT 24
Peak memory 200336 kb
Host smart-b0754bf3-0dd8-4e5f-99fd-9685047d2c00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912616751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.912616751
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_smoke.2481148741
Short name T421
Test name
Test status
Simulation time 683174944 ps
CPU time 9.53 seconds
Started Jul 07 05:31:56 PM PDT 24
Finished Jul 07 05:32:06 PM PDT 24
Peak memory 200296 kb
Host smart-6d06e0a0-8390-427d-902a-88393eba4e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481148741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2481148741
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2763717140
Short name T345
Test name
Test status
Simulation time 212573064705 ps
CPU time 1605.05 seconds
Started Jul 07 05:31:57 PM PDT 24
Finished Jul 07 05:58:43 PM PDT 24
Peak memory 716888 kb
Host smart-a6464d6e-3a3c-47c6-9738-7627b82a5d7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763717140 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2763717140
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1087631852
Short name T43
Test name
Test status
Simulation time 728615824 ps
CPU time 6.36 seconds
Started Jul 07 05:31:57 PM PDT 24
Finished Jul 07 05:32:04 PM PDT 24
Peak memory 200240 kb
Host smart-7ae54347-050e-44f8-8f74-9a153e2b0846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087631852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1087631852
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2322941463
Short name T45
Test name
Test status
Simulation time 14186939 ps
CPU time 0.66 seconds
Started Jul 07 05:31:59 PM PDT 24
Finished Jul 07 05:32:00 PM PDT 24
Peak memory 196888 kb
Host smart-494dc8e8-646e-422e-ac5b-b5843a5f3e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322941463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2322941463
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3167919976
Short name T445
Test name
Test status
Simulation time 2719705250 ps
CPU time 79.91 seconds
Started Jul 07 05:32:00 PM PDT 24
Finished Jul 07 05:33:20 PM PDT 24
Peak memory 200316 kb
Host smart-7ca86cfd-0525-44ff-b4a0-33afb0e52ec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167919976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3167919976
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1774216776
Short name T285
Test name
Test status
Simulation time 947471611 ps
CPU time 12.85 seconds
Started Jul 07 05:32:02 PM PDT 24
Finished Jul 07 05:32:15 PM PDT 24
Peak memory 200296 kb
Host smart-4f29eeac-eccb-4d9e-b87c-73ffa8d8707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774216776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1774216776
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_error.456349258
Short name T164
Test name
Test status
Simulation time 499767979 ps
CPU time 27.89 seconds
Started Jul 07 05:32:02 PM PDT 24
Finished Jul 07 05:32:30 PM PDT 24
Peak memory 200216 kb
Host smart-0e629870-70ba-494d-a5c5-b659f8624b1e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456349258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.456349258
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3889673612
Short name T323
Test name
Test status
Simulation time 2656791636 ps
CPU time 146.14 seconds
Started Jul 07 05:32:01 PM PDT 24
Finished Jul 07 05:34:28 PM PDT 24
Peak memory 200324 kb
Host smart-d7ac18e3-7f05-4504-9334-722c8199a527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889673612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3889673612
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2681031561
Short name T307
Test name
Test status
Simulation time 228716712 ps
CPU time 4.75 seconds
Started Jul 07 05:31:57 PM PDT 24
Finished Jul 07 05:32:02 PM PDT 24
Peak memory 200256 kb
Host smart-55c2743e-8e88-4da0-bdc5-8de528b922f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681031561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2681031561
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1035738816
Short name T372
Test name
Test status
Simulation time 20724246488 ps
CPU time 226.5 seconds
Started Jul 07 05:32:00 PM PDT 24
Finished Jul 07 05:35:47 PM PDT 24
Peak memory 200360 kb
Host smart-b571aae0-2ce1-418d-8eb1-105e2aaa643b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035738816 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1035738816
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.82721769
Short name T522
Test name
Test status
Simulation time 2125326476 ps
CPU time 13.05 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:32:12 PM PDT 24
Peak memory 200292 kb
Host smart-e3d65d7c-9776-41a7-91e8-5801144dbf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82721769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.82721769
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3767151109
Short name T406
Test name
Test status
Simulation time 11327441 ps
CPU time 0.58 seconds
Started Jul 07 05:32:03 PM PDT 24
Finished Jul 07 05:32:04 PM PDT 24
Peak memory 195104 kb
Host smart-a2eb11a5-acc3-4a21-8778-80a5601132a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767151109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3767151109
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2884130017
Short name T492
Test name
Test status
Simulation time 188723305 ps
CPU time 10.96 seconds
Started Jul 07 05:32:00 PM PDT 24
Finished Jul 07 05:32:11 PM PDT 24
Peak memory 200204 kb
Host smart-944ef53b-72eb-4fa3-a5a2-d88ea0e3e59f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884130017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2884130017
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.563338797
Short name T239
Test name
Test status
Simulation time 1765223977 ps
CPU time 34.93 seconds
Started Jul 07 05:32:03 PM PDT 24
Finished Jul 07 05:32:39 PM PDT 24
Peak memory 200320 kb
Host smart-5ec21aec-635e-4933-a4bf-cf2d93693e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563338797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.563338797
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1310505971
Short name T169
Test name
Test status
Simulation time 2206173415 ps
CPU time 316.74 seconds
Started Jul 07 05:32:00 PM PDT 24
Finished Jul 07 05:37:17 PM PDT 24
Peak memory 633304 kb
Host smart-448dffe3-2e66-4af6-84b4-046679ca60e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310505971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1310505971
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2556313649
Short name T388
Test name
Test status
Simulation time 12321547798 ps
CPU time 91.88 seconds
Started Jul 07 05:32:09 PM PDT 24
Finished Jul 07 05:33:41 PM PDT 24
Peak memory 200372 kb
Host smart-7beefc2c-995b-4d1a-b921-90de157760ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556313649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2556313649
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.4287437882
Short name T449
Test name
Test status
Simulation time 917439512 ps
CPU time 54.26 seconds
Started Jul 07 05:32:01 PM PDT 24
Finished Jul 07 05:32:55 PM PDT 24
Peak memory 200616 kb
Host smart-41708948-9938-44b6-b59f-7dd9f0aeea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287437882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.4287437882
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3248148979
Short name T506
Test name
Test status
Simulation time 54752352 ps
CPU time 0.92 seconds
Started Jul 07 05:31:58 PM PDT 24
Finished Jul 07 05:32:00 PM PDT 24
Peak memory 198960 kb
Host smart-44413a45-0720-45d3-b828-eb272919b436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248148979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3248148979
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1698403134
Short name T450
Test name
Test status
Simulation time 281096316697 ps
CPU time 3311.06 seconds
Started Jul 07 05:32:04 PM PDT 24
Finished Jul 07 06:27:16 PM PDT 24
Peak memory 790696 kb
Host smart-43dfac3d-6d04-4c58-855a-c5df21428645
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698403134 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1698403134
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.4190271059
Short name T508
Test name
Test status
Simulation time 2714756208 ps
CPU time 26.45 seconds
Started Jul 07 05:32:05 PM PDT 24
Finished Jul 07 05:32:32 PM PDT 24
Peak memory 200424 kb
Host smart-4bea25eb-8e4c-4d04-82f6-4dc1df9f714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190271059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.4190271059
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.4055957093
Short name T511
Test name
Test status
Simulation time 13818134 ps
CPU time 0.62 seconds
Started Jul 07 05:32:08 PM PDT 24
Finished Jul 07 05:32:09 PM PDT 24
Peak memory 196212 kb
Host smart-f0e6097e-2e89-46a6-ac93-45000fd95d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055957093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.4055957093
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1000456898
Short name T12
Test name
Test status
Simulation time 1669105769 ps
CPU time 100.53 seconds
Started Jul 07 05:32:06 PM PDT 24
Finished Jul 07 05:33:47 PM PDT 24
Peak memory 200280 kb
Host smart-51e0ab03-9e66-4b8f-b8e2-0ffa963cf3c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000456898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1000456898
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1104261158
Short name T144
Test name
Test status
Simulation time 7120792871 ps
CPU time 40.48 seconds
Started Jul 07 05:32:06 PM PDT 24
Finished Jul 07 05:32:47 PM PDT 24
Peak memory 200368 kb
Host smart-e143f74e-2f43-4000-b4e2-1b470a2c5418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104261158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1104261158
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1623988399
Short name T312
Test name
Test status
Simulation time 7490969251 ps
CPU time 698.72 seconds
Started Jul 07 05:32:06 PM PDT 24
Finished Jul 07 05:43:45 PM PDT 24
Peak memory 712428 kb
Host smart-0acd5378-88d3-4fd2-9b8f-72d10d29898c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1623988399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1623988399
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1537701310
Short name T277
Test name
Test status
Simulation time 380055248 ps
CPU time 21.75 seconds
Started Jul 07 05:32:05 PM PDT 24
Finished Jul 07 05:32:27 PM PDT 24
Peak memory 200288 kb
Host smart-37a8c2c0-5aac-4670-b625-bbbfc4a5184b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537701310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1537701310
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.4059627129
Short name T446
Test name
Test status
Simulation time 28531639380 ps
CPU time 129.61 seconds
Started Jul 07 05:32:06 PM PDT 24
Finished Jul 07 05:34:16 PM PDT 24
Peak memory 200552 kb
Host smart-7616fcd2-a767-4a66-8895-99173bed190b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059627129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.4059627129
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3196021469
Short name T221
Test name
Test status
Simulation time 304375873 ps
CPU time 13.47 seconds
Started Jul 07 05:32:05 PM PDT 24
Finished Jul 07 05:32:19 PM PDT 24
Peak memory 200324 kb
Host smart-4015698f-e83e-4fd3-abad-d70f20442fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196021469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3196021469
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.4069594242
Short name T96
Test name
Test status
Simulation time 25524568948 ps
CPU time 1580.3 seconds
Started Jul 07 05:32:12 PM PDT 24
Finished Jul 07 05:58:33 PM PDT 24
Peak memory 763172 kb
Host smart-f63e0f93-5aff-4697-9266-ae1a3696ab17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069594242 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.4069594242
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.538849150
Short name T211
Test name
Test status
Simulation time 4287807885 ps
CPU time 71.39 seconds
Started Jul 07 05:32:09 PM PDT 24
Finished Jul 07 05:33:21 PM PDT 24
Peak memory 200420 kb
Host smart-350414d3-2d28-4e92-959e-95cf1909bc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538849150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.538849150
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.123409443
Short name T373
Test name
Test status
Simulation time 21771465 ps
CPU time 0.57 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:31:09 PM PDT 24
Peak memory 196020 kb
Host smart-c2da7e9a-f076-46aa-aca9-b31246f8a64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123409443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.123409443
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2117285035
Short name T51
Test name
Test status
Simulation time 1161690443 ps
CPU time 64.63 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:32:07 PM PDT 24
Peak memory 200244 kb
Host smart-245617d7-32a8-4e51-92e0-521ddc605485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117285035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2117285035
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3440542631
Short name T484
Test name
Test status
Simulation time 10601189508 ps
CPU time 51.38 seconds
Started Jul 07 05:30:54 PM PDT 24
Finished Jul 07 05:31:45 PM PDT 24
Peak memory 200400 kb
Host smart-0047807b-e9d1-4693-bc1e-1a8f4040c41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440542631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3440542631
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2498480051
Short name T175
Test name
Test status
Simulation time 269094890 ps
CPU time 35.13 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:36 PM PDT 24
Peak memory 298180 kb
Host smart-ad3c698a-8979-44cb-92e1-a3e99468d195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498480051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2498480051
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3269536470
Short name T225
Test name
Test status
Simulation time 12451698904 ps
CPU time 167.88 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:33:38 PM PDT 24
Peak memory 200312 kb
Host smart-7fc85160-f4ba-446c-9658-2a425bfa4d7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269536470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3269536470
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.597231735
Short name T41
Test name
Test status
Simulation time 6965626996 ps
CPU time 53.19 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:31:58 PM PDT 24
Peak memory 200432 kb
Host smart-e7d6d105-ecfc-45df-9660-a1e7ea644d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597231735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.597231735
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.181965803
Short name T50
Test name
Test status
Simulation time 1441417282 ps
CPU time 17.31 seconds
Started Jul 07 05:30:51 PM PDT 24
Finished Jul 07 05:31:09 PM PDT 24
Peak memory 200304 kb
Host smart-4a06b7af-28fb-4343-8ae3-6438333a9c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181965803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.181965803
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3969084656
Short name T300
Test name
Test status
Simulation time 484359094371 ps
CPU time 2180.37 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 06:07:28 PM PDT 24
Peak memory 723788 kb
Host smart-f838baab-c503-492f-b6ed-cf7e23a8628c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969084656 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3969084656
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3433971643
Short name T20
Test name
Test status
Simulation time 93709666188 ps
CPU time 2252.62 seconds
Started Jul 07 05:31:07 PM PDT 24
Finished Jul 07 06:08:41 PM PDT 24
Peak memory 755400 kb
Host smart-4885df83-ee27-40fa-b680-7d926f0eed21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3433971643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3433971643
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.511281623
Short name T244
Test name
Test status
Simulation time 4319211371 ps
CPU time 20.04 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:31:25 PM PDT 24
Peak memory 200396 kb
Host smart-b28bb04b-c3e8-4b41-93e3-d82b38d9a836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511281623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.511281623
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.761445414
Short name T28
Test name
Test status
Simulation time 32844051 ps
CPU time 0.58 seconds
Started Jul 07 05:30:59 PM PDT 24
Finished Jul 07 05:31:00 PM PDT 24
Peak memory 195156 kb
Host smart-95c069a4-f23e-4b72-93b9-ebff71234e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761445414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.761445414
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3591911996
Short name T25
Test name
Test status
Simulation time 547920405 ps
CPU time 30.07 seconds
Started Jul 07 05:30:50 PM PDT 24
Finished Jul 07 05:31:21 PM PDT 24
Peak memory 200316 kb
Host smart-48b1d4f3-3cb5-41c2-baee-bc6424365c7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591911996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3591911996
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3557528028
Short name T246
Test name
Test status
Simulation time 3909316877 ps
CPU time 70.66 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:32:16 PM PDT 24
Peak memory 200380 kb
Host smart-5377497f-be8a-4379-b989-95c32e7d2f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557528028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3557528028
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2347364259
Short name T179
Test name
Test status
Simulation time 1711882756 ps
CPU time 276.65 seconds
Started Jul 07 05:30:54 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 469588 kb
Host smart-d7b30e95-72c7-4830-a2ba-630aaef214d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347364259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2347364259
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3201010122
Short name T271
Test name
Test status
Simulation time 1186627667 ps
CPU time 45.55 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:31:54 PM PDT 24
Peak memory 200224 kb
Host smart-0dc952c8-d70e-4b46-91b5-b71b81473e55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201010122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3201010122
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.691604487
Short name T228
Test name
Test status
Simulation time 1289456696 ps
CPU time 69.47 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:32:11 PM PDT 24
Peak memory 200304 kb
Host smart-66274789-0573-482d-af81-c008ec245fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691604487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.691604487
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3228221594
Short name T139
Test name
Test status
Simulation time 1015827599 ps
CPU time 12.78 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:31:16 PM PDT 24
Peak memory 200280 kb
Host smart-c07d7934-46f3-49cb-9790-03073e0a85ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228221594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3228221594
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.185124501
Short name T78
Test name
Test status
Simulation time 56655658999 ps
CPU time 617.64 seconds
Started Jul 07 05:30:58 PM PDT 24
Finished Jul 07 05:41:16 PM PDT 24
Peak memory 256800 kb
Host smart-dfb984af-0d0b-4987-bbd9-5c9115a3ac39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185124501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.185124501
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.231208577
Short name T249
Test name
Test status
Simulation time 12016638686 ps
CPU time 37.42 seconds
Started Jul 07 05:30:59 PM PDT 24
Finished Jul 07 05:31:36 PM PDT 24
Peak memory 200360 kb
Host smart-3aed074a-b8ab-4bc4-b974-fcaa890ca797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231208577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.231208577
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2447634597
Short name T332
Test name
Test status
Simulation time 86961265 ps
CPU time 0.63 seconds
Started Jul 07 05:30:59 PM PDT 24
Finished Jul 07 05:31:00 PM PDT 24
Peak memory 195160 kb
Host smart-b6953fa6-7c7e-4216-a8de-24c5db25fcf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447634597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2447634597
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3779156205
Short name T405
Test name
Test status
Simulation time 314708016 ps
CPU time 17.35 seconds
Started Jul 07 05:30:51 PM PDT 24
Finished Jul 07 05:31:09 PM PDT 24
Peak memory 200328 kb
Host smart-a56b589b-a724-4d73-b9db-945dead4c2a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779156205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3779156205
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3294248857
Short name T183
Test name
Test status
Simulation time 941794147 ps
CPU time 5.29 seconds
Started Jul 07 05:30:59 PM PDT 24
Finished Jul 07 05:31:05 PM PDT 24
Peak memory 200340 kb
Host smart-41367e9f-92ac-464e-8df2-5bd2f759684a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294248857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3294248857
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.345540079
Short name T186
Test name
Test status
Simulation time 4374718761 ps
CPU time 913.61 seconds
Started Jul 07 05:30:53 PM PDT 24
Finished Jul 07 05:46:07 PM PDT 24
Peak memory 689220 kb
Host smart-af50728c-383f-4352-ba36-5e3747ff03e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=345540079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.345540079
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1950808504
Short name T174
Test name
Test status
Simulation time 5132914487 ps
CPU time 283.75 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:35:48 PM PDT 24
Peak memory 200312 kb
Host smart-c547d1d5-bd40-42fc-a397-fe8f825d2a6f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950808504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1950808504
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2238095465
Short name T5
Test name
Test status
Simulation time 16957509383 ps
CPU time 56.25 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:32:00 PM PDT 24
Peak memory 200516 kb
Host smart-c81979f8-c32c-474b-a4f5-1a45e8ad3c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238095465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2238095465
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2759986661
Short name T495
Test name
Test status
Simulation time 10274524908 ps
CPU time 14.18 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:31:19 PM PDT 24
Peak memory 200260 kb
Host smart-f6248a74-ea75-4613-ab93-296ccd60ea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759986661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2759986661
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.4274023023
Short name T260
Test name
Test status
Simulation time 44440347693 ps
CPU time 697.51 seconds
Started Jul 07 05:31:09 PM PDT 24
Finished Jul 07 05:42:47 PM PDT 24
Peak memory 483352 kb
Host smart-e5448a8c-9984-477f-b075-6e42bd3dfe3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274023023 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.4274023023
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1355057261
Short name T433
Test name
Test status
Simulation time 11961165428 ps
CPU time 15.01 seconds
Started Jul 07 05:31:07 PM PDT 24
Finished Jul 07 05:31:23 PM PDT 24
Peak memory 200248 kb
Host smart-35772b7d-7dcb-48b1-9003-9d927dabb4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355057261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1355057261
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3630647451
Short name T329
Test name
Test status
Simulation time 18863182 ps
CPU time 0.59 seconds
Started Jul 07 05:30:52 PM PDT 24
Finished Jul 07 05:30:53 PM PDT 24
Peak memory 196212 kb
Host smart-1168b9b2-ff4e-4e94-ba8c-52c65d27875e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630647451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3630647451
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.592736572
Short name T319
Test name
Test status
Simulation time 1317537856 ps
CPU time 37.26 seconds
Started Jul 07 05:31:09 PM PDT 24
Finished Jul 07 05:31:47 PM PDT 24
Peak memory 200328 kb
Host smart-c12baba4-0b14-47d9-8c76-53c387b657a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=592736572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.592736572
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3482329545
Short name T487
Test name
Test status
Simulation time 1037544162 ps
CPU time 3.32 seconds
Started Jul 07 05:30:56 PM PDT 24
Finished Jul 07 05:31:00 PM PDT 24
Peak memory 200260 kb
Host smart-6349d3fc-80b7-4ca1-8032-0bc42efcdc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482329545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3482329545
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.828122836
Short name T318
Test name
Test status
Simulation time 26459086547 ps
CPU time 1416.68 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:54:32 PM PDT 24
Peak memory 668464 kb
Host smart-fa5d1b78-2f90-4496-88d3-e179d5788905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828122836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.828122836
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2197123739
Short name T247
Test name
Test status
Simulation time 16076793759 ps
CPU time 173.91 seconds
Started Jul 07 05:30:59 PM PDT 24
Finished Jul 07 05:33:53 PM PDT 24
Peak memory 200300 kb
Host smart-cb58faac-bcd9-411e-9ea9-00cb9be6ec58
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197123739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2197123739
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3864827875
Short name T410
Test name
Test status
Simulation time 13916338244 ps
CPU time 53.99 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:31:49 PM PDT 24
Peak memory 200400 kb
Host smart-006989c6-9c6c-4c44-935e-35d0e5d8fb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864827875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3864827875
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.317379751
Short name T442
Test name
Test status
Simulation time 87875660 ps
CPU time 1.56 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:31:06 PM PDT 24
Peak memory 200228 kb
Host smart-d107877c-5acf-44b3-91e1-580c5f6e3f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317379751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.317379751
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1908021849
Short name T26
Test name
Test status
Simulation time 30252262766 ps
CPU time 3404.12 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 06:27:51 PM PDT 24
Peak memory 785832 kb
Host smart-230d0a98-0255-47eb-87b8-b703494c9fea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908021849 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1908021849
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1038395132
Short name T238
Test name
Test status
Simulation time 4595982289 ps
CPU time 54.09 seconds
Started Jul 07 05:31:02 PM PDT 24
Finished Jul 07 05:31:57 PM PDT 24
Peak memory 200420 kb
Host smart-a3b72789-3c99-4b4e-859c-5ffd1a2ec19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038395132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1038395132
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3147478998
Short name T242
Test name
Test status
Simulation time 35665584 ps
CPU time 0.62 seconds
Started Jul 07 05:31:03 PM PDT 24
Finished Jul 07 05:31:04 PM PDT 24
Peak memory 196168 kb
Host smart-5bf4adab-c0da-4dba-8884-05f25a1936ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147478998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3147478998
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.4262913009
Short name T261
Test name
Test status
Simulation time 976916205 ps
CPU time 54.87 seconds
Started Jul 07 05:31:04 PM PDT 24
Finished Jul 07 05:32:00 PM PDT 24
Peak memory 200384 kb
Host smart-7ffed2b3-ff87-4cf2-948c-d09684bad35d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262913009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.4262913009
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.934670526
Short name T146
Test name
Test status
Simulation time 349017622 ps
CPU time 18.83 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:31:21 PM PDT 24
Peak memory 200372 kb
Host smart-c565f1ad-da04-4825-a5aa-78d9ab0ca246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934670526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.934670526
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3388405233
Short name T299
Test name
Test status
Simulation time 5269332190 ps
CPU time 356.58 seconds
Started Jul 07 05:31:12 PM PDT 24
Finished Jul 07 05:37:09 PM PDT 24
Peak memory 665840 kb
Host smart-79499151-03ab-4ee8-a2d9-499c0770d0fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388405233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3388405233
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3683477354
Short name T58
Test name
Test status
Simulation time 5844633182 ps
CPU time 23.57 seconds
Started Jul 07 05:30:55 PM PDT 24
Finished Jul 07 05:31:19 PM PDT 24
Peak memory 200384 kb
Host smart-1b0e506a-fdac-4f77-869b-3d34a7f88ec7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683477354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3683477354
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3247934993
Short name T428
Test name
Test status
Simulation time 9548820317 ps
CPU time 147.31 seconds
Started Jul 07 05:31:08 PM PDT 24
Finished Jul 07 05:33:37 PM PDT 24
Peak memory 200380 kb
Host smart-833d9c27-c981-4b06-967f-e22049ed4d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247934993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3247934993
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3152865312
Short name T474
Test name
Test status
Simulation time 4194712265 ps
CPU time 15.67 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:31:23 PM PDT 24
Peak memory 200400 kb
Host smart-9b20ec30-34cc-4bb2-8ca9-0571da464d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152865312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3152865312
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1429524655
Short name T395
Test name
Test status
Simulation time 66767983043 ps
CPU time 960.29 seconds
Started Jul 07 05:31:01 PM PDT 24
Finished Jul 07 05:47:03 PM PDT 24
Peak memory 467128 kb
Host smart-01c6c1d9-b549-4e1b-a35f-4acf9126d046
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429524655 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1429524655
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.404000366
Short name T22
Test name
Test status
Simulation time 15223534694 ps
CPU time 279.05 seconds
Started Jul 07 05:31:00 PM PDT 24
Finished Jul 07 05:35:39 PM PDT 24
Peak memory 354584 kb
Host smart-c45c9e6b-787c-4e61-9cc3-04c8daf1fd86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=404000366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.404000366
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.87795898
Short name T160
Test name
Test status
Simulation time 5935053520 ps
CPU time 26.64 seconds
Started Jul 07 05:31:06 PM PDT 24
Finished Jul 07 05:31:33 PM PDT 24
Peak memory 200392 kb
Host smart-379b03ef-ee40-4fc5-8966-3f596a76a789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87795898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.87795898
Directory /workspace/9.hmac_wipe_secret/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%