Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46015876	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

43577705

1

T1

22851

T2

456599

T3

16866

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	42601554	1			T1	24762		T2	466876		T3	19030
values[0x0]	21945227	1			T1	11384		T2	228848		T3	8684
values[0x1]	25046800	1			T1	13212		T2	261202		T3	10157

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35316716	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

54276865

1

T1

28929

T2

569635

T3

21586

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	374812	1			T1	182		T3	154		T4	14
valid_sources[0x01]	265929	1			T1	205		T3	165		T4	30
valid_sources[0x02]	277573	1			T1	184		T3	136		T4	24
valid_sources[0x03]	629733	1			T1	190		T3	139		T4	78
valid_sources[0x04]	266724	1			T1	198		T2	1		T3	150
valid_sources[0x05]	266127	1			T1	217		T3	140		T4	43
valid_sources[0x06]	803923	1			T1	167		T3	147		T4	17
valid_sources[0x07]	268547	1			T1	224		T3	166		T4	17
valid_sources[0x08]	264829	1			T1	206		T3	161		T4	33
valid_sources[0x09]	266896	1			T1	183		T3	145		T4	25
valid_sources[0x0a]	781680	1			T1	158		T3	142		T4	46
valid_sources[0x0b]	266718	1			T1	193		T3	172		T4	19
valid_sources[0x0c]	265567	1			T1	205		T3	130		T4	33
valid_sources[0x0d]	268447	1			T1	202		T3	172		T4	64
valid_sources[0x0e]	269946	1			T1	215		T3	136		T4	33
valid_sources[0x0f]	264814	1			T1	190		T3	157		T4	26
valid_sources[0x10]	367585	1			T1	218		T3	126		T4	45
valid_sources[0x11]	267256	1			T1	186		T3	164		T4	29
valid_sources[0x12]	275258	1			T1	214		T3	144		T4	37
valid_sources[0x13]	267122	1			T1	176		T3	190		T4	46
valid_sources[0x14]	266209	1			T1	191		T3	167		T4	22
valid_sources[0x15]	270838	1			T1	184		T3	163		T4	47
valid_sources[0x16]	276722	1			T1	204		T3	165		T4	29
valid_sources[0x17]	360054	1			T1	179		T3	117		T4	77
valid_sources[0x18]	276183	1			T1	176		T3	150		T4	63
valid_sources[0x19]	277113	1			T1	214		T3	149		T4	34
valid_sources[0x1a]	472780	1			T1	219		T3	182		T4	47
valid_sources[0x1b]	267022	1			T1	191		T3	174		T4	45
valid_sources[0x1c]	267885	1			T1	181		T3	148		T4	26
valid_sources[0x1d]	264624	1			T1	190		T3	162		T4	39
valid_sources[0x1e]	283303	1			T1	173		T3	198		T4	36
valid_sources[0x1f]	265500	1			T1	201		T3	160		T4	41
valid_sources[0x20]	266096	1			T1	215		T3	161		T4	52
valid_sources[0x21]	266734	1			T1	182		T3	157		T4	20
valid_sources[0x22]	315791	1			T1	176		T3	169		T4	52
valid_sources[0x23]	263298	1			T1	226		T3	138		T4	43
valid_sources[0x24]	268338	1			T1	188		T3	125		T4	30
valid_sources[0x25]	266120	1			T1	186		T3	121		T4	62
valid_sources[0x26]	263890	1			T1	194		T3	150		T4	40
valid_sources[0x27]	268809	1			T1	161		T3	166		T4	35
valid_sources[0x28]	276808	1			T1	188		T3	137		T4	43
valid_sources[0x29]	390456	1			T1	193		T3	160		T4	6
valid_sources[0x2a]	269482	1			T1	235		T3	126		T4	9
valid_sources[0x2b]	270858	1			T1	212		T3	167		T4	55
valid_sources[0x2c]	273421	1			T1	176		T3	131		T4	11
valid_sources[0x2d]	268337	1			T1	196		T3	140		T4	54
valid_sources[0x2e]	265005	1			T1	197		T3	182		T4	46
valid_sources[0x2f]	270221	1			T1	166		T3	110		T4	29
valid_sources[0x30]	265346	1			T1	202		T3	128		T4	21
valid_sources[0x31]	2216462	1			T1	181		T3	153		T4	48
valid_sources[0x32]	269706	1			T1	171		T3	151		T4	53
valid_sources[0x33]	264715	1			T1	166		T3	117		T4	60
valid_sources[0x34]	295057	1			T1	167		T3	148		T4	34
valid_sources[0x35]	264789	1			T1	203		T3	141		T4	8
valid_sources[0x36]	264683	1			T1	202		T3	127		T4	24
valid_sources[0x37]	329641	1			T1	204		T3	152		T4	19
valid_sources[0x38]	268587	1			T1	196		T3	156		T4	20
valid_sources[0x39]	265891	1			T1	185		T3	116		T4	11
valid_sources[0x3a]	267759	1			T1	182		T3	117		T4	38
valid_sources[0x3b]	286014	1			T1	207		T3	157		T4	29
valid_sources[0x3c]	265783	1			T1	182		T3	128		T5	399
valid_sources[0x3d]	310236	1			T1	162		T3	170		T4	36
valid_sources[0x3e]	269739	1			T1	206		T3	181		T4	41
valid_sources[0x3f]	263894	1			T1	160		T3	155		T4	29
valid_sources[0x40]	1732375	1			T1	202		T3	152		T4	44
valid_sources[0x41]	268274	1			T1	205		T3	142		T4	13
valid_sources[0x42]	265577	1			T1	188		T3	134		T4	16
valid_sources[0x43]	277508	1			T1	213		T3	114		T4	54
valid_sources[0x44]	270040	1			T1	203		T2	1		T3	170
valid_sources[0x45]	272307	1			T1	171		T3	135		T4	66
valid_sources[0x46]	280453	1			T1	203		T3	121		T4	47
valid_sources[0x47]	484956	1			T1	211		T2	199603		T3	158
valid_sources[0x48]	263486	1			T1	159		T3	152		T4	31
valid_sources[0x49]	268648	1			T1	218		T3	149		T4	21
valid_sources[0x4a]	268239	1			T1	166		T3	156		T4	12
valid_sources[0x4b]	277681	1			T1	165		T3	178		T4	54
valid_sources[0x4c]	378628	1			T1	219		T3	158		T4	15
valid_sources[0x4d]	263042	1			T1	197		T3	113		T4	13
valid_sources[0x4e]	271543	1			T1	192		T3	137		T4	31
valid_sources[0x4f]	273993	1			T1	202		T3	146		T4	42
valid_sources[0x50]	397638	1			T1	230		T2	1		T3	174
valid_sources[0x51]	426294	1			T1	172		T3	178		T4	13
valid_sources[0x52]	269950	1			T1	205		T3	153		T4	79
valid_sources[0x53]	369633	1			T1	155		T3	96		T4	10
valid_sources[0x54]	301318	1			T1	159		T3	122		T4	53
valid_sources[0x55]	269036	1			T1	185		T3	125		T4	20
valid_sources[0x56]	268483	1			T1	181		T3	149		T4	12
valid_sources[0x57]	267382	1			T1	214		T3	146		T4	41
valid_sources[0x58]	286772	1			T1	193		T3	141		T4	22
valid_sources[0x59]	272000	1			T1	212		T3	111		T4	33
valid_sources[0x5a]	264530	1			T1	192		T3	143		T4	30
valid_sources[0x5b]	367983	1			T1	216		T3	124		T4	40
valid_sources[0x5c]	391602	1			T1	170		T3	174		T4	68
valid_sources[0x5d]	976493	1			T1	170		T2	1		T3	151
valid_sources[0x5e]	666695	1			T1	187		T3	152		T4	27
valid_sources[0x5f]	266585	1			T1	166		T3	177		T4	37
valid_sources[0x60]	267076	1			T1	189		T3	147		T4	40
valid_sources[0x61]	267363	1			T1	201		T3	153		T4	65
valid_sources[0x62]	264944	1			T1	201		T3	147		T4	20
valid_sources[0x63]	263865	1			T1	149		T3	103		T4	33
valid_sources[0x64]	267094	1			T1	212		T3	146		T4	18
valid_sources[0x65]	265774	1			T1	179		T3	142		T4	30
valid_sources[0x66]	328314	1			T1	174		T3	135		T4	26
valid_sources[0x67]	266651	1			T1	197		T3	139		T4	30
valid_sources[0x68]	321869	1			T1	169		T2	1		T3	112
valid_sources[0x69]	268778	1			T1	191		T3	136		T4	35
valid_sources[0x6a]	270120	1			T1	177		T3	116		T4	52
valid_sources[0x6b]	430424	1			T1	148		T3	127		T4	22
valid_sources[0x6c]	282619	1			T1	232		T3	168		T4	49
valid_sources[0x6d]	269321	1			T1	198		T3	130		T4	21
valid_sources[0x6e]	264326	1			T1	157		T3	136		T4	10
valid_sources[0x6f]	306595	1			T1	212		T3	128		T4	22
valid_sources[0x70]	265961	1			T1	191		T3	134		T4	14
valid_sources[0x71]	2333186	1			T1	173		T3	130		T4	25
valid_sources[0x72]	267484	1			T1	194		T3	157		T4	14
valid_sources[0x73]	270244	1			T1	229		T3	188		T4	33
valid_sources[0x74]	274732	1			T1	211		T3	200		T4	47
valid_sources[0x75]	270514	1			T1	208		T3	119		T4	5
valid_sources[0x76]	266870	1			T1	183		T3	150		T4	50
valid_sources[0x77]	268886	1			T1	196		T3	137		T4	37
valid_sources[0x78]	274551	1			T1	198		T3	137		T4	32
valid_sources[0x79]	267294	1			T1	221		T3	106		T4	31
valid_sources[0x7a]	267661	1			T1	188		T3	139		T4	34
valid_sources[0x7b]	266459	1			T1	187		T3	120		T4	15
valid_sources[0x7c]	269253	1			T1	221		T3	163		T4	48
valid_sources[0x7d]	268056	1			T1	193		T3	129		T4	35
valid_sources[0x7e]	268122	1			T1	239		T3	167		T4	16
valid_sources[0x7f]	265912	1			T1	213		T3	139		T4	35
valid_sources[0x80]	307782	1			T1	173		T3	169		T4	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21099557

1

T1

12274

T2

232607

T3

9416

values[0x0]

all_enables

biggest_size

12101705

1

T1

5733

T2

121118

T3

4123

values[0x1]

all_enables

biggest_size

10376443

1

T1

4844

T2

102874

T3

3327