Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

51480192

1

T1

26507

T2

500327

T3

21005

full_word

43933340

1

T1

22851

T2

456599

T3

16866

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	95413132	1			T1	49358		T2	956926		T3	37871
auto[TlIntgErrCmd]	148	1			T60	10		T61	16		T62	7
auto[TlIntgErrData]	115	1			T60	10		T61	7		T62	7
auto[TlIntgErrBoth]	137	1			T60	10		T61	7		T62	16

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44446967

1

T1

24762

T2

466876

T3

19030

auto[1]

50966565

1

T1

24596

T2

490050

T3

18841

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23206843	1			T1	12488		T2	234269		T3	9614
auto[TlIntgErrNone]	partial	auto[1]	28272980	1			T1	14019		T2	266058		T3	11391
auto[TlIntgErrNone]	full_word	auto[0]	21239951	1			T1	12274		T2	232607		T3	9416
auto[TlIntgErrNone]	full_word	auto[1]	22693358	1			T1	10577		T2	223992		T3	7450
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T60	3		T61	7		T62	3
auto[TlIntgErrCmd]	partial	auto[1]	89	1			T60	7		T61	7		T62	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T61	2		T119	1		T123	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T121	2		T63	1		T124	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T60	4		T61	6		T62	2
auto[TlIntgErrData]	partial	auto[1]	46	1			T60	2		T61	1		T62	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T60	3		T122	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T60	1		T62	2		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T60	6		T61	1		T62	8
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T60	4		T61	5		T62	8
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T122	1		T126	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T61	1		T119	1		T127	1