Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	477094822	3115645	0	0
intr_enable_rd_A	477094822	2208	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477094822	3115645	0	0
T7	704082	125672	0	0
T8	0	243754	0	0
T9	0	6626	0	0
T12	0	168041	0	0
T19	0	225658	0	0
T20	0	400170	0	0
T21	0	36191	0	0
T22	10986	0	0	0
T25	24401	0	0	0
T39	182547	0	0	0
T42	0	438242	0	0
T44	741304	0	0	0
T45	1148	0	0	0
T64	0	96111	0	0
T65	0	72878	0	0
T66	35063	0	0	0
T67	31597	0	0	0
T68	375230	0	0	0
T69	60104	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	477094822	2208	0	0
T2	100865	24	0	0
T3	401207	0	0	0
T4	62734	0	0	0
T5	207571	0	0	0
T6	773601	21	0	0
T7	704082	57	0	0
T13	76483	0	0	0
T14	609058	0	0	0
T15	54625	0	0	0
T16	1157	0	0	0
T28	0	44	0	0
T70	0	99	0	0
T71	0	27	0	0
T72	0	9	0	0
T73	0	32	0	0
T74	0	7	0	0
T75	0	10	0	0