Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48055003

1

T1

316

T2

72855

T3

3

full_word

42024395

1

T1

437

T2

62139

T3

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	90079028	1			T1	753		T2	134994		T3	6
auto[TlIntgErrCmd]	106	1			T52	4		T53	8		T54	2
auto[TlIntgErrData]	112	1			T53	8		T54	5		T100	11
auto[TlIntgErrBoth]	152	1			T52	6		T53	14		T54	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42402814

1

T1

392

T2

66151

T3

1

auto[1]

47676584

1

T1

361

T2

68843

T3

5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21882165	1			T1	200		T2	33187		T4	8346
auto[TlIntgErrNone]	partial	auto[1]	26172502	1			T1	116		T2	39668		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	20520486	1			T1	192		T2	32964		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	21503875	1			T1	245		T2	29175		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T52	2		T53	4		T54	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T52	2		T53	4		T54	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T102	1		T103	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T104	2		T105	2		T106	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T53	5		T54	2		T100	5
auto[TlIntgErrData]	partial	auto[1]	47	1			T53	2		T54	2		T100	6
auto[TlIntgErrData]	full_word	auto[0]	6	1			T53	1		T54	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T108	2		T109	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T52	2		T53	4		T54	1
auto[TlIntgErrBoth]	partial	auto[1]	85	1			T52	3		T53	9		T54	2
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T53	1		T100	1		T104	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T52	1		T104	1		T105	3