Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	483534442	1969722	0	0
intr_enable_rd_A	483534442	3306	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483534442	1969722	0	0
T10	994890	341850	0	0
T11	0	97887	0	0
T12	0	28091	0	0
T16	0	312298	0	0
T21	0	352641	0	0
T22	0	110314	0	0
T43	3238	0	0	0
T55	0	112625	0	0
T56	0	162376	0	0
T57	0	31564	0	0
T58	0	694	0	0
T59	265631	0	0	0
T60	724755	0	0	0
T61	606971	0	0	0
T62	89989	0	0	0
T63	616608	0	0	0
T64	201457	0	0	0
T65	662462	0	0	0
T66	435206	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483534442	3306	0	0
T5	786465	22	0	0
T6	62550	0	0	0
T11	0	154	0	0
T12	0	11	0	0
T19	152671	0	0	0
T25	89000	0	0	0
T35	691477	0	0	0
T39	933661	0	0	0
T42	7143	0	0	0
T47	41220	0	0	0
T48	106720	0	0	0
T60	0	15	0	0
T67	0	6	0	0
T68	0	12	0	0
T69	0	12	0	0
T70	0	68	0	0
T71	0	13	0	0
T72	0	8	0	0
T73	1180	0	0	0