Module Definition
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Module : prim_packer
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.10 100.00 93.75 86.67 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_packer 97.51 100.00 93.75 96.30 100.00



Module Instance : tb.dut.u_packer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.51 100.00 93.75 96.30 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.51 100.00 93.75 96.30 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.71 100.00 93.33 100.00 100.00 98.90 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_packer
Line No.TotalCoveredPercent
TOTAL6666100.00
ALWAYS6533100.00
CONT_ASSIGN7211100.00
ALWAYS7866100.00
ALWAYS9055100.00
ALWAYS15744100.00
CONT_ASSIGN16511100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN18011100.00
ALWAYS18599100.00
ALWAYS21488100.00
ALWAYS23533100.00
ALWAYS2431414100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN29100
CONT_ASSIGN29411100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
72 1 1
78 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
90 1 1
91 1 1
92 1 1
93 1 1
95 1 1
157 1 1
158 1 1
159 1 1
160 1 1
MISSING_ELSE
165 1 1
166 1 1
170 1 1
171 1 1
174 1 1
175 1 1
178 1 1
180 1 1
185 1 1
187 1 1
188 1 1
192 1 1
193 1 1
197 1 1
198 1 1
202 1 1
203 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
221 1 1
222 1 1
235 1 1
236 1 1
238 1 1
243 1 1
245 1 1
246 1 1
248 1 1
250 1 1
251 1 1
253 1 1
258 1 1
259 1 1
261 1 1
262 1 1
264 1 1
266 1 1
267 1 1
279 1 1
283 1 1
291 unreachable
294 1 1
295 1 1
296 1 1
299 unreachable


Cond Coverage for Module : prim_packer
TotalCoveredPercent
Conditions161593.75
Logical161593.75
Non-Logical00
Event00

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 7'(OutW))))
             ----------1----------
-1-StatusTests
0UnreachableT1,T2,T4
1CoveredT1,T2,T4

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 7'(OutW))))
             ---------------1--------------
-1-StatusTests
0UnreachableT13,T24,T14
1Not Covered

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT13,T14,T15
11CoveredT1,T2,T4

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T24,T14
11CoveredT1,T2,T4

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1UnreachableT1,T2,T4

Branch Coverage for Module : prim_packer
Line No.TotalCoveredPercent
Branches 30 26 86.67
TERNARY 170 2 2 100.00
TERNARY 171 2 2 100.00
TERNARY 283 1 1 100.00
IF 159 2 2 100.00
CASE 185 5 4 80.00
IF 214 3 3 100.00
IF 235 2 2 100.00
CASE 248 5 4 80.00
CASE 80 5 3 60.00
IF 90 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 170 (valid_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 171 (valid_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 283 ((int'(pos_q) >= OutW)) ?

Branches:
-1-StatusTests
1 Unreachable T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 159 if ((mask_i[i] == 1'b1))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 185 case ({ack_in, ack_out})

Branches:
-1-StatusTests
2'b00 Covered T1,T2,T3
2'b01 Covered T1,T2,T4
2'b10 Covered T1,T2,T4
2'b11 Covered T13,T24,T14
default Not Covered


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 217 if (flush_done)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 235 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 248 case (flush_st) -2-: 250 if (flush_i) -3-: 258 if ((pos_q == '0))

Branches:
-1--2--3-StatusTests
FlushIdle 1 - Covered T1,T2,T4
FlushIdle 0 - Covered T1,T2,T3
FlushSend - 1 Covered T1,T2,T4
FlushSend - 0 Covered T1,T2,T4
default - - Not Covered


LineNo. Expression -1-: 80 case ({ack_in, ack_out}) -2-: 82 ((int'(pos_q) <= OutW)) ? -3-: 84 ((int'(pos_with_input) <= OutW)) ?

Branches:
-1--2--3-StatusTests
2'b00 - - Covered T1,T2,T3
2'b01 1 - Covered T1,T2,T4
2'b01 0 - Unreachable T1,T2,T4
2'b10 - - Covered T1,T2,T4
2'b11 - 1 Not Covered
2'b11 - 0 Unreachable T13,T24,T14
default - - Not Covered


LineNo. Expression -1-: 90 if ((!rst_ni)) -2-: 92 if (flush_done)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T4
0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_packer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 10 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 10 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataIStable_M 467348690 64 0 492
DataOStableWhenPending_A 467348690 112 0 492
ExFlushValid_M 467348690 17887 0 0
ExcessiveDataStored_A 467348690 4 0 0
ExcessiveMaskStored_A 467348690 4 0 0
FlushFollowedByDone_A 467348690 17887 0 492
ValidIDeassertedOnFlush_M 467348690 28840 0 0
ValidOAssertedForStoredDataGTEOutW_A 467348690 7651654 0 0
ValidOPairedWidthReadyI_A 467348690 112 0 0
gen_mask_assert.ContiguousOnesMask_M 467348690 10018018 0 0


DataIStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 64 0 492
T13 264279 5 0 1
T14 0 10 0 0
T15 0 49 0 0
T26 105074 0 0 1
T27 143689 0 0 1
T28 28095 0 0 1
T29 1111 0 0 1
T30 879 0 0 1
T31 536418 0 0 1
T32 4872 0 0 1
T33 464929 0 0 1
T34 402886 0 0 1

DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 112 0 492
T13 264279 18 0 1
T14 0 12 0 0
T15 0 75 0 0
T24 0 7 0 0
T26 105074 0 0 1
T27 143689 0 0 1
T28 28095 0 0 1
T29 1111 0 0 1
T30 879 0 0 1
T31 536418 0 0 1
T32 4872 0 0 1
T33 464929 0 0 1
T34 402886 0 0 1

ExFlushValid_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 17887 0 0
T1 9136 3 0 0
T2 948258 6 0 0
T3 700 0 0 0
T4 80567 13 0 0
T5 786465 95 0 0
T7 141274 386 0 0
T8 203478 23 0 0
T9 93128 7 0 0
T17 634521 19 0 0
T18 17118 13 0 0
T25 0 2 0 0

ExcessiveDataStored_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 4 0 0
T13 264279 1 0 0
T14 0 1 0 0
T15 0 1 0 0
T24 0 1 0 0
T26 105074 0 0 0
T27 143689 0 0 0
T28 28095 0 0 0
T29 1111 0 0 0
T30 879 0 0 0
T31 536418 0 0 0
T32 4872 0 0 0
T33 464929 0 0 0
T34 402886 0 0 0

ExcessiveMaskStored_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 4 0 0
T13 264279 1 0 0
T14 0 1 0 0
T15 0 1 0 0
T24 0 1 0 0
T26 105074 0 0 0
T27 143689 0 0 0
T28 28095 0 0 0
T29 1111 0 0 0
T30 879 0 0 0
T31 536418 0 0 0
T32 4872 0 0 0
T33 464929 0 0 0
T34 402886 0 0 0

FlushFollowedByDone_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 17887 0 492
T1 9136 3 0 1
T2 948258 6 0 1
T3 700 0 0 1
T4 80567 13 0 1
T5 786465 95 0 1
T7 141274 386 0 1
T8 203478 23 0 1
T9 93128 7 0 1
T17 634521 19 0 1
T18 17118 13 0 1
T25 0 2 0 0

ValidIDeassertedOnFlush_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 28840 0 0
T1 9136 4 0 0
T2 948258 11 0 0
T3 700 0 0 0
T4 80567 23 0 0
T5 786465 170 0 0
T7 141274 674 0 0
T8 203478 39 0 0
T9 93128 12 0 0
T17 634521 32 0 0
T18 17118 20 0 0
T25 0 4 0 0

ValidOAssertedForStoredDataGTEOutW_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 7651654 0 0
T1 9136 16 0 0
T2 948258 5084 0 0
T3 700 0 0 0
T4 80567 5340 0 0
T5 786465 59958 0 0
T6 0 2102 0 0
T7 141274 212416 0 0
T8 203478 8148 0 0
T9 93128 2493 0 0
T17 634521 7078 0 0
T18 17118 283 0 0

ValidOPairedWidthReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 112 0 0
T13 264279 18 0 0
T14 0 12 0 0
T15 0 75 0 0
T24 0 7 0 0
T26 105074 0 0 0
T27 143689 0 0 0
T28 28095 0 0 0
T29 1111 0 0 0
T30 879 0 0 0
T31 536418 0 0 0
T32 4872 0 0 0
T33 464929 0 0 0
T34 402886 0 0 0

gen_mask_assert.ContiguousOnesMask_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 10018018 0 0
T1 9136 21 0 0
T2 948258 7012 0 0
T3 700 0 0 0
T4 80567 5678 0 0
T5 786465 81263 0 0
T7 141274 294228 0 0
T8 203478 11325 0 0
T9 93128 3446 0 0
T17 634521 9767 0 0
T18 17118 401 0 0
T25 0 2 0 0

Line Coverage for Instance : tb.dut.u_packer
Line No.TotalCoveredPercent
TOTAL6666100.00
ALWAYS6533100.00
CONT_ASSIGN7211100.00
ALWAYS7866100.00
ALWAYS9055100.00
ALWAYS15744100.00
CONT_ASSIGN16511100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN18011100.00
ALWAYS18599100.00
ALWAYS21488100.00
ALWAYS23533100.00
ALWAYS2431414100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN29100
CONT_ASSIGN29411100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
66 1 1
67 1 1
72 1 1
78 1 1
80 1 1
81 1 1
82 1 1
83 1 1
84 1 1
Exclude Annotation: VC_COV_UNR
90 1 1
91 1 1
92 1 1
93 1 1
95 1 1
157 1 1
158 1 1
159 1 1
160 1 1
MISSING_ELSE
165 1 1
166 1 1
170 1 1
171 1 1
174 1 1
175 1 1
178 1 1
180 1 1
185 1 1
187 1 1
188 1 1
192 1 1
193 1 1
197 1 1
198 1 1
202 1 1
203 1 1
Exclude Annotation: VC_COV_UNR
Exclude Annotation: VC_COV_UNR
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
221 1 1
222 1 1
235 1 1
236 1 1
238 1 1
243 1 1
245 1 1
246 1 1
248 1 1
250 1 1
251 1 1
253 1 1
258 1 1
259 1 1
261 1 1
262 1 1
264 1 1
266 1 1
267 1 1
Exclude Annotation: VC_COV_UNR
Exclude Annotation: VC_COV_UNR
Exclude Annotation: VC_COV_UNR
279 1 1
283 1 1
291 unreachable
294 1 1
295 1 1
296 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_packer
TotalCoveredPercent
Conditions161593.75
Logical161593.75
Non-Logical00
Event00

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 7'(OutW))))
             ----------1----------
-1-StatusTests
0UnreachableT1,T2,T4
1CoveredT1,T2,T4

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 7'(OutW))))
             ---------------1--------------
-1-StatusTests
0UnreachableT13,T24,T14
1Not Covered

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT13,T14,T15
11CoveredT1,T2,T4

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T24,T14
11CoveredT1,T2,T4

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T4

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1UnreachableT1,T2,T4

Branch Coverage for Instance : tb.dut.u_packer
Line No.TotalCoveredPercent
Branches 27 26 96.30
TERNARY 170 2 2 100.00
TERNARY 171 2 2 100.00
TERNARY 283 1 1 100.00
IF 159 2 2 100.00
CASE 185 4 4 100.00
IF 214 3 3 100.00
IF 235 2 2 100.00
CASE 248 4 4 100.00
CASE 80 4 3 75.00
IF 90 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 170 (valid_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 171 (valid_i) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 283 ((int'(pos_q) >= OutW)) ?

Branches:
-1-StatusTests
1 Unreachable T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 159 if ((mask_i[i] == 1'b1))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 185 case ({ack_in, ack_out})

Branches:
-1-StatusTestsExclude Annotation
2'b00 Covered T1,T2,T3
2'b01 Covered T1,T2,T4
2'b10 Covered T1,T2,T4
2'b11 Covered T13,T24,T14
default Excluded VC_COV_UNR


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 217 if (flush_done)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 235 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 248 case (flush_st) -2-: 250 if (flush_i) -3-: 258 if ((pos_q == '0))

Branches:
-1--2--3-StatusTestsExclude Annotation
FlushIdle 1 - Covered T1,T2,T4
FlushIdle 0 - Covered T1,T2,T3
FlushSend - 1 Covered T1,T2,T4
FlushSend - 0 Covered T1,T2,T4
default - - Excluded VC_COV_UNR


LineNo. Expression -1-: 80 case ({ack_in, ack_out}) -2-: 82 ((int'(pos_q) <= OutW)) ? -3-: 84 ((int'(pos_with_input) <= OutW)) ?

Branches:
-1--2--3-StatusTestsExclude Annotation
2'b00 - - Covered T1,T2,T3
2'b01 1 - Covered T1,T2,T4
2'b01 0 - Unreachable T1,T2,T4
2'b10 - - Covered T1,T2,T4
2'b11 - 1 Not Covered
2'b11 - 0 Unreachable T13,T24,T14
default - - Excluded VC_COV_UNR


LineNo. Expression -1-: 90 if ((!rst_ni)) -2-: 92 if (flush_done)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T4
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_packer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 10 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 10 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataIStable_M 467348690 64 0 492
DataOStableWhenPending_A 467348690 112 0 492
ExFlushValid_M 467348690 17887 0 0
ExcessiveDataStored_A 467348690 4 0 0
ExcessiveMaskStored_A 467348690 4 0 0
FlushFollowedByDone_A 467348690 17887 0 492
ValidIDeassertedOnFlush_M 467348690 28840 0 0
ValidOAssertedForStoredDataGTEOutW_A 467348690 7651654 0 0
ValidOPairedWidthReadyI_A 467348690 112 0 0
gen_mask_assert.ContiguousOnesMask_M 467348690 10018018 0 0


DataIStable_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 64 0 492
T13 264279 5 0 1
T14 0 10 0 0
T15 0 49 0 0
T26 105074 0 0 1
T27 143689 0 0 1
T28 28095 0 0 1
T29 1111 0 0 1
T30 879 0 0 1
T31 536418 0 0 1
T32 4872 0 0 1
T33 464929 0 0 1
T34 402886 0 0 1

DataOStableWhenPending_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 112 0 492
T13 264279 18 0 1
T14 0 12 0 0
T15 0 75 0 0
T24 0 7 0 0
T26 105074 0 0 1
T27 143689 0 0 1
T28 28095 0 0 1
T29 1111 0 0 1
T30 879 0 0 1
T31 536418 0 0 1
T32 4872 0 0 1
T33 464929 0 0 1
T34 402886 0 0 1

ExFlushValid_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 17887 0 0
T1 9136 3 0 0
T2 948258 6 0 0
T3 700 0 0 0
T4 80567 13 0 0
T5 786465 95 0 0
T7 141274 386 0 0
T8 203478 23 0 0
T9 93128 7 0 0
T17 634521 19 0 0
T18 17118 13 0 0
T25 0 2 0 0

ExcessiveDataStored_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 4 0 0
T13 264279 1 0 0
T14 0 1 0 0
T15 0 1 0 0
T24 0 1 0 0
T26 105074 0 0 0
T27 143689 0 0 0
T28 28095 0 0 0
T29 1111 0 0 0
T30 879 0 0 0
T31 536418 0 0 0
T32 4872 0 0 0
T33 464929 0 0 0
T34 402886 0 0 0

ExcessiveMaskStored_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 4 0 0
T13 264279 1 0 0
T14 0 1 0 0
T15 0 1 0 0
T24 0 1 0 0
T26 105074 0 0 0
T27 143689 0 0 0
T28 28095 0 0 0
T29 1111 0 0 0
T30 879 0 0 0
T31 536418 0 0 0
T32 4872 0 0 0
T33 464929 0 0 0
T34 402886 0 0 0

FlushFollowedByDone_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 17887 0 492
T1 9136 3 0 1
T2 948258 6 0 1
T3 700 0 0 1
T4 80567 13 0 1
T5 786465 95 0 1
T7 141274 386 0 1
T8 203478 23 0 1
T9 93128 7 0 1
T17 634521 19 0 1
T18 17118 13 0 1
T25 0 2 0 0

ValidIDeassertedOnFlush_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 28840 0 0
T1 9136 4 0 0
T2 948258 11 0 0
T3 700 0 0 0
T4 80567 23 0 0
T5 786465 170 0 0
T7 141274 674 0 0
T8 203478 39 0 0
T9 93128 12 0 0
T17 634521 32 0 0
T18 17118 20 0 0
T25 0 4 0 0

ValidOAssertedForStoredDataGTEOutW_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 7651654 0 0
T1 9136 16 0 0
T2 948258 5084 0 0
T3 700 0 0 0
T4 80567 5340 0 0
T5 786465 59958 0 0
T6 0 2102 0 0
T7 141274 212416 0 0
T8 203478 8148 0 0
T9 93128 2493 0 0
T17 634521 7078 0 0
T18 17118 283 0 0

ValidOPairedWidthReadyI_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 112 0 0
T13 264279 18 0 0
T14 0 12 0 0
T15 0 75 0 0
T24 0 7 0 0
T26 105074 0 0 0
T27 143689 0 0 0
T28 28095 0 0 0
T29 1111 0 0 0
T30 879 0 0 0
T31 536418 0 0 0
T32 4872 0 0 0
T33 464929 0 0 0
T34 402886 0 0 0

gen_mask_assert.ContiguousOnesMask_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 467348690 10018018 0 0
T1 9136 21 0 0
T2 948258 7012 0 0
T3 700 0 0 0
T4 80567 5678 0 0
T5 786465 81263 0 0
T7 141274 294228 0 0
T8 203478 11325 0 0
T9 93128 3446 0 0
T17 634521 9767 0 0
T18 17118 401 0 0
T25 0 2 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%