Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42275972	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40481555

1

T1

4051

T2

6

T3

33613

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39256191	1			T1	4029		T2	1		T3	38558
values[0x0]	20390124	1			T1	1695		T2	10		T3	17249
values[0x1]	23111212	1			T1	1992		T2	10		T3	20902

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32507440	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50250087

1

T1

4867

T2

7

T3

43658

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	221765	1			T1	21		T4	1030		T8	3
valid_sources[0x01]	347264	1			T1	41		T4	1033		T8	4
valid_sources[0x02]	298796	1			T1	33		T4	1028		T8	9
valid_sources[0x03]	218472	1			T1	38		T4	1032		T8	11
valid_sources[0x04]	218101	1			T1	39		T4	960		T8	4
valid_sources[0x05]	292233	1			T1	41		T4	1031		T8	5
valid_sources[0x06]	220815	1			T1	28		T4	1048		T8	9
valid_sources[0x07]	237694	1			T1	27		T4	978		T8	5
valid_sources[0x08]	443881	1			T1	38		T4	1001		T8	7
valid_sources[0x09]	218777	1			T1	28		T4	1029		T8	2
valid_sources[0x0a]	219478	1			T1	26		T4	1022		T8	2
valid_sources[0x0b]	221932	1			T1	34		T4	1013		T8	8
valid_sources[0x0c]	221437	1			T1	28		T4	1028		T8	5
valid_sources[0x0d]	219796	1			T1	27		T4	1041		T8	4
valid_sources[0x0e]	404393	1			T1	36		T4	1017		T8	5
valid_sources[0x0f]	267511	1			T1	26		T4	952		T8	8
valid_sources[0x10]	218581	1			T1	32		T4	1009		T8	6
valid_sources[0x11]	370849	1			T1	39		T4	994		T8	5
valid_sources[0x12]	219109	1			T1	18		T4	1031		T8	10
valid_sources[0x13]	217986	1			T1	31		T4	1026		T8	7
valid_sources[0x14]	218777	1			T1	20		T4	990		T8	4
valid_sources[0x15]	219228	1			T1	32		T4	980		T8	10
valid_sources[0x16]	219533	1			T1	24		T4	1021		T8	5
valid_sources[0x17]	248043	1			T1	32		T4	1039		T8	8
valid_sources[0x18]	224326	1			T1	33		T4	1038		T8	8
valid_sources[0x19]	228280	1			T1	37		T4	993		T8	3
valid_sources[0x1a]	220514	1			T1	21		T4	1026		T8	3
valid_sources[0x1b]	434138	1			T1	34		T4	1055		T8	4
valid_sources[0x1c]	219269	1			T1	28		T4	957		T8	2
valid_sources[0x1d]	219738	1			T1	25		T4	1002		T8	4
valid_sources[0x1e]	218020	1			T1	30		T4	981		T8	10
valid_sources[0x1f]	220618	1			T1	34		T4	1010		T8	6
valid_sources[0x20]	219912	1			T1	23		T4	1001		T8	9
valid_sources[0x21]	218233	1			T1	24		T4	979		T8	5
valid_sources[0x22]	687378	1			T1	33		T4	996		T8	12
valid_sources[0x23]	216971	1			T1	24		T4	973		T8	3
valid_sources[0x24]	219575	1			T1	32		T4	1030		T8	9
valid_sources[0x25]	231962	1			T1	26		T4	1017		T8	7
valid_sources[0x26]	239920	1			T1	38		T4	968		T8	5
valid_sources[0x27]	235076	1			T1	31		T4	1037		T8	9
valid_sources[0x28]	761900	1			T1	31		T4	1010		T8	2
valid_sources[0x29]	1003460	1			T1	32		T4	982		T8	7
valid_sources[0x2a]	225562	1			T1	36		T4	984		T8	5
valid_sources[0x2b]	243409	1			T1	29		T4	996		T8	9
valid_sources[0x2c]	552768	1			T1	27		T4	987		T8	9
valid_sources[0x2d]	221936	1			T1	29		T4	1051		T8	16
valid_sources[0x2e]	488251	1			T1	29		T4	1025		T8	7
valid_sources[0x2f]	218183	1			T1	32		T4	1030		T8	4
valid_sources[0x30]	219468	1			T1	26		T4	1084		T8	10
valid_sources[0x31]	219243	1			T1	44		T4	981		T8	2
valid_sources[0x32]	219417	1			T1	39		T4	1022		T8	7
valid_sources[0x33]	220488	1			T1	25		T4	1009		T7	157
valid_sources[0x34]	234886	1			T1	35		T4	983		T8	8
valid_sources[0x35]	219474	1			T1	21		T4	982		T8	8
valid_sources[0x36]	218509	1			T1	27		T4	1004		T8	6
valid_sources[0x37]	220524	1			T1	23		T4	1074		T8	9
valid_sources[0x38]	219784	1			T1	40		T4	1038		T8	9
valid_sources[0x39]	271621	1			T1	21		T4	1010		T8	6
valid_sources[0x3a]	219721	1			T1	23		T4	1023		T8	1
valid_sources[0x3b]	296368	1			T1	21		T3	76709		T4	994
valid_sources[0x3c]	217223	1			T1	26		T4	971		T8	9
valid_sources[0x3d]	226365	1			T1	25		T4	1004		T8	5
valid_sources[0x3e]	217223	1			T1	33		T4	981		T8	8
valid_sources[0x3f]	220503	1			T1	26		T4	993		T8	3
valid_sources[0x40]	216121	1			T1	26		T4	1007		T8	7
valid_sources[0x41]	220218	1			T1	42		T4	978		T8	11
valid_sources[0x42]	323367	1			T1	17		T4	1018		T8	6
valid_sources[0x43]	217216	1			T1	37		T4	1012		T8	4
valid_sources[0x44]	219346	1			T1	33		T4	998		T8	3
valid_sources[0x45]	367775	1			T1	39		T4	1058		T8	6
valid_sources[0x46]	218722	1			T1	28		T4	1020		T8	8
valid_sources[0x47]	228018	1			T1	39		T4	1037		T8	4
valid_sources[0x48]	221902	1			T1	22		T4	998		T8	7
valid_sources[0x49]	220054	1			T1	30		T4	1036		T8	3
valid_sources[0x4a]	217920	1			T1	26		T4	983		T8	2
valid_sources[0x4b]	220378	1			T1	22		T4	1038		T8	7
valid_sources[0x4c]	221495	1			T1	33		T4	946		T8	9
valid_sources[0x4d]	218789	1			T1	38		T4	1040		T8	2
valid_sources[0x4e]	218947	1			T1	30		T4	1012		T8	7
valid_sources[0x4f]	330992	1			T1	34		T4	971		T8	6
valid_sources[0x50]	222539	1			T1	34		T4	1028		T8	3
valid_sources[0x51]	219374	1			T1	28		T4	980		T8	3
valid_sources[0x52]	596437	1			T1	30		T4	1021		T8	4
valid_sources[0x53]	393688	1			T1	34		T4	1019		T8	10
valid_sources[0x54]	320283	1			T1	29		T4	974		T8	6
valid_sources[0x55]	220662	1			T1	27		T4	1021		T8	9
valid_sources[0x56]	220913	1			T1	27		T4	1020		T8	5
valid_sources[0x57]	276047	1			T1	21		T4	1010		T8	5
valid_sources[0x58]	218442	1			T1	33		T4	1017		T8	5
valid_sources[0x59]	219298	1			T1	26		T4	1026		T8	8
valid_sources[0x5a]	216732	1			T1	49		T4	1012		T8	12
valid_sources[0x5b]	217381	1			T1	18		T4	953		T8	5
valid_sources[0x5c]	218957	1			T1	16		T4	1048		T8	8
valid_sources[0x5d]	218439	1			T1	30		T4	964		T8	6
valid_sources[0x5e]	219712	1			T1	28		T4	993		T8	10
valid_sources[0x5f]	304883	1			T1	40		T4	1012		T8	9
valid_sources[0x60]	221119	1			T1	26		T4	972		T8	5
valid_sources[0x61]	220535	1			T1	30		T4	971		T8	4
valid_sources[0x62]	227297	1			T1	30		T4	955		T8	4
valid_sources[0x63]	285621	1			T1	31		T4	1057		T8	7
valid_sources[0x64]	367857	1			T1	32		T4	1010		T8	7
valid_sources[0x65]	229646	1			T1	31		T4	1016		T8	9
valid_sources[0x66]	218331	1			T1	22		T4	1059		T8	5
valid_sources[0x67]	218244	1			T1	33		T4	1007		T8	4
valid_sources[0x68]	219946	1			T1	28		T4	991		T8	4
valid_sources[0x69]	220357	1			T1	38		T4	1057		T8	6
valid_sources[0x6a]	217487	1			T1	31		T4	962		T8	8
valid_sources[0x6b]	217704	1			T1	28		T4	1002		T8	5
valid_sources[0x6c]	295113	1			T1	40		T4	1046		T8	11
valid_sources[0x6d]	225334	1			T1	45		T4	1014		T8	4
valid_sources[0x6e]	218634	1			T1	31		T4	957		T8	6
valid_sources[0x6f]	2307751	1			T1	25		T4	1034		T8	2
valid_sources[0x70]	217725	1			T1	29		T4	1015		T8	8
valid_sources[0x71]	2100197	1			T1	41		T4	992		T8	2
valid_sources[0x72]	231933	1			T1	33		T4	1031		T8	6
valid_sources[0x73]	299262	1			T1	24		T4	940		T8	6
valid_sources[0x74]	218605	1			T1	25		T4	995		T8	4
valid_sources[0x75]	221912	1			T1	31		T4	1044		T8	6
valid_sources[0x76]	289182	1			T1	43		T4	1018		T8	1
valid_sources[0x77]	220482	1			T1	33		T4	1021		T8	8
valid_sources[0x78]	252872	1			T1	25		T4	1024		T8	6
valid_sources[0x79]	221122	1			T1	38		T4	1015		T8	3
valid_sources[0x7a]	220744	1			T1	47		T4	1028		T8	5
valid_sources[0x7b]	221525	1			T1	25		T4	1011		T8	9
valid_sources[0x7c]	218830	1			T1	34		T4	991		T8	8
valid_sources[0x7d]	219266	1			T1	33		T4	992		T8	5
valid_sources[0x7e]	219932	1			T1	29		T4	1049		T8	7
valid_sources[0x7f]	315523	1			T1	32		T4	1024		T8	4
valid_sources[0x80]	219302	1			T1	36		T4	997		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19415646

1

T1

1963

T2

1

T3

19191

values[0x0]

all_enables

biggest_size

11335758

1

T1

1035

T2

2

T3

7968

values[0x1]

all_enables

biggest_size

9730151

1

T1

1053

T2

3

T3

6454