Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

46110283

1

T1

3665

T2

15

T3

43096

full_word

40730175

1

T1

4051

T2

6

T3

33613

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	86840098	1			T1	7716		T2	21		T3	76709
auto[TlIntgErrCmd]	125	1			T56	4		T57	5		T58	11
auto[TlIntgErrData]	126	1			T56	4		T57	2		T58	10
auto[TlIntgErrBoth]	109	1			T56	2		T57	3		T58	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40532012

1

T1

4029

T2

1

T3

38558

auto[1]

46308446

1

T1

3687

T2

20

T3

38151

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21018965	1			T1	2066		T3	19367		T4	65362
auto[TlIntgErrNone]	partial	auto[1]	25090988	1			T1	1599		T2	15		T3	23729
auto[TlIntgErrNone]	full_word	auto[0]	19512868	1			T1	1963		T2	1		T3	19191
auto[TlIntgErrNone]	full_word	auto[1]	21217277	1			T1	2088		T2	5		T3	14422
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T56	2		T57	2		T58	4
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T56	2		T57	3		T58	7
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T59	1		T116	1		T117	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T113	1		T118	2		T115	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T56	4		T57	1		T58	3
auto[TlIntgErrData]	partial	auto[1]	56	1			T57	1		T58	6		T111	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T111	1		T61	1		T115	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T58	1		T114	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T56	1		T57	2		T58	4
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T56	1		T58	5		T111	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T57	1		T111	2		T114	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T114	1		T59	2		T112	1