Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	434955930	2202433	0	0
intr_enable_rd_A	434955930	2250	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434955930	2202433	0	0
T9	610280	229104	0	0
T10	0	145211	0	0
T11	0	203821	0	0
T13	960908	0	0	0
T16	0	33911	0	0
T17	0	61487	0	0
T18	0	131411	0	0
T21	90420	0	0	0
T22	114639	0	0	0
T23	0	237725	0	0
T29	148490	0	0	0
T41	147934	0	0	0
T42	1086	0	0	0
T62	0	104363	0	0
T63	0	67831	0	0
T64	0	117154	0	0
T65	21718	0	0	0
T66	12393	0	0	0
T67	3136	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434955930	2250	0	0
T6	267369	0	0	0
T9	610280	0	0	0
T16	0	124	0	0
T17	0	42	0	0
T18	0	183	0	0
T20	483588	4	0	0
T21	90420	0	0	0
T22	114639	0	0	0
T24	63185	0	0	0
T41	147934	0	0	0
T42	1086	0	0	0
T65	21718	0	0	0
T66	12393	0	0	0
T68	0	5	0	0
T69	0	16	0	0
T70	0	45	0	0
T71	0	35	0	0
T72	0	10	0	0
T73	0	25	0	0