SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
86.88 | 93.33 | 54.17 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_tlul_adapter.u_rspfifo | 84.64 | 92.86 | 100.00 | 85.71 | 60.00 | ||
tb.dut.u_tlul_adapter.u_sramreqfifo | 86.43 | 85.71 | 100.00 | 100.00 | 60.00 | ||
tb.dut.u_msg_fifo | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | ||
tb.dut.u_tlul_adapter.u_reqfifo | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | ||
tb.dut.u_reg.u_socket.fifo_h.reqfifo | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_reg.u_socket.fifo_h.rspfifo | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
84.64 | 92.86 | 100.00 | 85.71 | 60.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
87.20 | 97.14 | 100.00 | 91.67 | 60.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.80 | 98.57 | 100.00 | 100.00 | 84.62 | u_tlul_adapter |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
86.43 | 85.71 | 100.00 | 100.00 | 60.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
88.57 | 94.29 | 100.00 | 100.00 | 60.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.80 | 98.57 | 100.00 | 100.00 | 84.62 | u_tlul_adapter |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.71 | 100.00 | 93.33 | 100.00 | 100.00 | 98.90 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.80 | 98.57 | 100.00 | 100.00 | 84.62 | u_tlul_adapter |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_normal_fifo.u_fifo_cnt | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | fifo_h |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | fifo_h |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[0].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[0].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[1].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | gen_dfifo[1].fifo_d |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 14 | 14 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
120 | 1 | 1 | |
123 | 1 | 1 | |
124 | 1 | 1 | |
MISSING_ELSE | |||
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
SCORE | LINE |
86.43 | 85.71 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 12 | 80.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 1 | 50.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 0 | 1 | |
111 | 1 | 1 | |
112 | 0 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 0 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
SCORE | LINE |
84.64 | 92.86 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 13 | 86.67 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 1 | 50.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 0 | 1 | |
111 | 1 | 1 | |
112 | 0 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
SCORE | COND |
86.43 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 5 | 31.25 |
Logical | 16 | 5 | 31.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
SCORE | COND |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 24 | 20 | 83.33 |
Logical | 24 | 20 | 83.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T9,T13,T25 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T14,T15 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
SCORE | COND |
84.64 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 24 | 8 | 33.33 |
Logical | 24 | 8 | 33.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Not Covered |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
SCORE | COND |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
---|---|---|---|---|
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T8,T12 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
SCORE | BRANCH |
100.00 | 100.00 |
SCORE | BRANCH |
84.64 | 85.71 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 9 | 9 | 100.00 | |
TERNARY | 130 | 2 | 2 | 100.00 |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 123 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T3,T4 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T3,T4 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T3,T4 |
0 | Covered | T1,T2,T3 |
SCORE | BRANCH |
100.00 | 100.00 |
SCORE | BRANCH |
86.43 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 7 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T3,T4 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T3,T4 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 6 | 6 | 100.00 | 6 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 6 | 6 | 100.00 | 6 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 2147483647 | 525149361 | 0 | 0 |
DepthKnown_A | 2147483647 | 2147483647 | 0 | 0 |
RvalidKnown_A | 2147483647 | 2147483647 | 0 | 0 |
WreadyKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 1642641192 | 55136410 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 3954 | 3954 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 525149361 | 0 | 0 |
T1 | 162728 | 34314 | 0 | 0 |
T2 | 8976 | 84 | 0 | 0 |
T3 | 1249056 | 330060 | 0 | 0 |
T4 | 4192224 | 1157628 | 0 | 0 |
T5 | 431176 | 133447 | 0 | 0 |
T6 | 0 | 122102 | 0 | 0 |
T7 | 600592 | 166230 | 0 | 0 |
T8 | 141792 | 18299 | 0 | 0 |
T12 | 487368 | 130956 | 0 | 0 |
T19 | 7944 | 286 | 0 | 0 |
T20 | 3868704 | 2419748 | 0 | 0 |
T24 | 0 | 39128 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 203410 | 202850 | 0 | 0 |
T2 | 11220 | 10460 | 0 | 0 |
T3 | 1561320 | 1560710 | 0 | 0 |
T4 | 5240280 | 5239640 | 0 | 0 |
T5 | 538970 | 538470 | 0 | 0 |
T7 | 750740 | 749810 | 0 | 0 |
T8 | 177240 | 176480 | 0 | 0 |
T12 | 609210 | 608570 | 0 | 0 |
T19 | 9930 | 9190 | 0 | 0 |
T20 | 4835880 | 4835490 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 203410 | 202850 | 0 | 0 |
T2 | 11220 | 10460 | 0 | 0 |
T3 | 1561320 | 1560710 | 0 | 0 |
T4 | 5240280 | 5239640 | 0 | 0 |
T5 | 538970 | 538470 | 0 | 0 |
T7 | 750740 | 749810 | 0 | 0 |
T8 | 177240 | 176480 | 0 | 0 |
T12 | 609210 | 608570 | 0 | 0 |
T19 | 9930 | 9190 | 0 | 0 |
T20 | 4835880 | 4835490 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 203410 | 202850 | 0 | 0 |
T2 | 11220 | 10460 | 0 | 0 |
T3 | 1561320 | 1560710 | 0 | 0 |
T4 | 5240280 | 5239640 | 0 | 0 |
T5 | 538970 | 538470 | 0 | 0 |
T7 | 750740 | 749810 | 0 | 0 |
T8 | 177240 | 176480 | 0 | 0 |
T12 | 609210 | 608570 | 0 | 0 |
T19 | 9930 | 9190 | 0 | 0 |
T20 | 4835880 | 4835490 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1642641192 | 55136410 | 0 | 0 |
T1 | 40682 | 3450 | 0 | 0 |
T2 | 2244 | 0 | 0 | 0 |
T3 | 312264 | 23224 | 0 | 0 |
T4 | 1048056 | 124752 | 0 | 0 |
T5 | 107794 | 30987 | 0 | 0 |
T6 | 0 | 56354 | 0 | 0 |
T7 | 150148 | 19082 | 0 | 0 |
T8 | 35448 | 1453 | 0 | 0 |
T12 | 121842 | 12236 | 0 | 0 |
T19 | 1986 | 0 | 0 | 0 |
T20 | 967176 | 623899 | 0 | 0 |
T24 | 0 | 20478 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 3954 | 3954 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T8 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
T19 | 6 | 6 | 0 | 0 |
T20 | 6 | 6 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 14 | 13 | 92.86 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 0 | 1 | |
111 | 1 | 1 | |
112 | excluded | ||
Exclude Annotation: VC_COV_UNR | |||
MISSING_ELSE | |||
116 | 1 | 1 | |
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | Covered | T1,T2,T3 | |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Excluded | VC_COV_UNR |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Excluded | VC_COV_UNR |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Excluded | VC_COV_UNR |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests | Exclude Annotation |
---|---|---|---|
0 | Covered | T1,T2,T3 | |
1 | Excluded | VC_COV_UNR |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | Covered | T1,T2,T3 | |
1 | 1 | Excluded | VC_COV_UNR |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests | Exclude Annotation |
---|---|---|---|
0 | Excluded | VC_COV_UNR | |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 6 | 85.71 | |
TERNARY | 130 | 1 | 1 | 100.00 |
TERNARY | 138 | 1 | 1 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 123 | 2 | 1 | 50.00 |
LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
-1- | Status | Tests | Exclude Annotation |
---|---|---|---|
1 | Excluded | VC_COV_UNR | |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests | Exclude Annotation |
---|---|---|---|
1 | Covered | T1,T2,T3 | |
0 | Excluded | VC_COV_UNR |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Not Covered | |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 3 | 60.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 3 | 60.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 410660298 | 0 | 0 | 0 |
DepthKnown_A | 410660298 | 410596470 | 0 | 0 |
RvalidKnown_A | 410660298 | 410596470 | 0 | 0 |
WreadyKnown_A | 410660298 | 410596470 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 410660298 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 14 | 12 | 85.71 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 1 | 1 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 0 | 1 | |
111 | 1 | 1 | |
112 | excluded | ||
Exclude Annotation: VC_COV_UNR | |||
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 0 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 5 | 5 | 100.00 |
Logical | 5 | 5 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | Covered | T1,T2,T3 | |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Excluded | VC_COV_UNR |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Excluded | VC_COV_UNR |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Excluded | VC_COV_UNR |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests | Exclude Annotation |
---|---|---|---|
0 | Excluded | VC_COV_UNR | |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 5 | 5 | 100.00 | |
TERNARY | 138 | 1 | 1 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 1 | 1 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests | Exclude Annotation |
---|---|---|---|
1 | Covered | T1,T2,T3 | |
0 | Excluded | VC_COV_UNR |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests | Exclude Annotation |
---|---|---|---|
1 | Excluded | VC_COV_UNR | |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 3 | 60.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 3 | 60.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 410660298 | 0 | 0 | 0 |
DepthKnown_A | 410660298 | 410596470 | 0 | 0 |
RvalidKnown_A | 410660298 | 410596470 | 0 | 0 |
WreadyKnown_A | 410660298 | 410596470 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 410660298 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 14 | 14 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
120 | 1 | 1 | |
123 | 1 | 1 | |
124 | 1 | 1 | |
MISSING_ELSE | |||
130 | 1 | 1 | |
131 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 20 | 20 | 100.00 |
Logical | 20 | 20 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T9,T13,T25 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T3,T4 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Covered | T13,T14,T15 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Covered | T1,T3,T4 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 130 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata) --------------------1-------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T4 |
LINE 130 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i) -------------1------------ ----2---
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T4 |
LINE 131 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i))) -------------1------------ ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 9 | 9 | 100.00 | |
TERNARY | 130 | 2 | 2 | 100.00 |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 123 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T3,T4 |
0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T3,T4 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T3,T4 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 410660298 | 22529756 | 0 | 0 |
DepthKnown_A | 410660298 | 410596470 | 0 | 0 |
RvalidKnown_A | 410660298 | 410596470 | 0 | 0 |
WreadyKnown_A | 410660298 | 410596470 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 410660298 | 22529756 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 22529756 | 0 | 0 |
T1 | 20341 | 2233 | 0 | 0 |
T2 | 1122 | 0 | 0 | 0 |
T3 | 156132 | 4370 | 0 | 0 |
T4 | 524028 | 61377 | 0 | 0 |
T5 | 53897 | 21600 | 0 | 0 |
T6 | 0 | 23480 | 0 | 0 |
T7 | 75074 | 9990 | 0 | 0 |
T8 | 17724 | 451 | 0 | 0 |
T12 | 60921 | 5055 | 0 | 0 |
T19 | 993 | 0 | 0 | 0 |
T20 | 483588 | 101387 | 0 | 0 |
T24 | 0 | 5188 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 22529756 | 0 | 0 |
T1 | 20341 | 2233 | 0 | 0 |
T2 | 1122 | 0 | 0 | 0 |
T3 | 156132 | 4370 | 0 | 0 |
T4 | 524028 | 61377 | 0 | 0 |
T5 | 53897 | 21600 | 0 | 0 |
T6 | 0 | 23480 | 0 | 0 |
T7 | 75074 | 9990 | 0 | 0 |
T8 | 17724 | 451 | 0 | 0 |
T12 | 60921 | 5055 | 0 | 0 |
T19 | 993 | 0 | 0 | 0 |
T20 | 483588 | 101387 | 0 | 0 |
T24 | 0 | 5188 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 15 | 15 | 100.00 | |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
69 | 1 | 1 | |
70 | 1 | 1 | |
71 | 1 | 1 | |
72 | 1 | 1 | |
MISSING_ELSE | |||
81 | 1 | 1 | |
82 | 1 | 1 | |
100 | 1 | 1 | |
101 | 1 | 1 | |
108 | 1 | 1 | |
111 | 1 | 1 | |
112 | 1 | 1 | |
MISSING_ELSE | |||
116 | 1 | 1 | |
133 | 1 | 1 | |
134 | 1 | 1 | |
138 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 11 | 11 | 100.00 |
Logical | 11 | 11 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 81 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst))) -----1----- ---------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) -------------1------------ ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
---|---|---|---|---|
0 | 1 | Covered | T1,T2,T3 | |
1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | Covered | T1,T3,T4 |
LINE 100 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Covered | T1,T2,T3 | |
1 | 0 | 1 | Excluded | VC_COV_UNR | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 101 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) ----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
---|---|---|---|---|---|
0 | 1 | 1 | Excluded | VC_COV_UNR | |
1 | 0 | 1 | Covered | T1,T8,T12 | |
1 | 1 | 0 | Excluded | VC_COV_UNR | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 138 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int) ----------1----------
-1- | Status | Tests |
---|---|---|
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 7 | 7 | 100.00 | |
TERNARY | 138 | 2 | 2 | 100.00 |
IF | 69 | 3 | 3 | 100.00 |
IF | 111 | 2 | 2 | 100.00 |
LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T2,T3 |
0 | Covered | T1,T3,T4 |
LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | - | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
0 | 0 | Covered | T1,T2,T3 |
LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
-1- | Status | Tests |
---|---|---|
1 | Covered | T1,T3,T4 |
0 | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 410660298 | 32606654 | 0 | 0 |
DepthKnown_A | 410660298 | 410596470 | 0 | 0 |
RvalidKnown_A | 410660298 | 410596470 | 0 | 0 |
WreadyKnown_A | 410660298 | 410596470 | 0 | 0 |
gen_normal_fifo.depthShallNotExceedParamDepth | 410660298 | 32606654 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 32606654 | 0 | 0 |
T1 | 20341 | 1217 | 0 | 0 |
T2 | 1122 | 0 | 0 | 0 |
T3 | 156132 | 18854 | 0 | 0 |
T4 | 524028 | 63375 | 0 | 0 |
T5 | 53897 | 9387 | 0 | 0 |
T6 | 0 | 32874 | 0 | 0 |
T7 | 75074 | 9092 | 0 | 0 |
T8 | 17724 | 1002 | 0 | 0 |
T12 | 60921 | 7181 | 0 | 0 |
T19 | 993 | 0 | 0 | 0 |
T20 | 483588 | 522512 | 0 | 0 |
T24 | 0 | 15290 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 410596470 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 410660298 | 32606654 | 0 | 0 |
T1 | 20341 | 1217 | 0 | 0 |
T2 | 1122 | 0 | 0 | 0 |
T3 | 156132 | 18854 | 0 | 0 |
T4 | 524028 | 63375 | 0 | 0 |
T5 | 53897 | 9387 | 0 | 0 |
T6 | 0 | 32874 | 0 | 0 |
T7 | 75074 | 9092 | 0 | 0 |
T8 | 17724 | 1002 | 0 | 0 |
T12 | 60921 | 7181 | 0 | 0 |
T19 | 993 | 0 | 0 | 0 |
T20 | 483588 | 522512 | 0 | 0 |
T24 | 0 | 15290 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 434955930 | 96714101 | 0 | 0 |
DepthKnown_A | 434955930 | 434851178 | 0 | 0 |
RvalidKnown_A | 434955930 | 434851178 | 0 | 0 |
WreadyKnown_A | 434955930 | 434851178 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 659 | 659 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 96714101 | 0 | 0 |
T1 | 20341 | 7716 | 0 | 0 |
T2 | 1122 | 21 | 0 | 0 |
T3 | 156132 | 76709 | 0 | 0 |
T4 | 524028 | 258219 | 0 | 0 |
T5 | 53897 | 25615 | 0 | 0 |
T7 | 75074 | 36787 | 0 | 0 |
T8 | 17724 | 1524 | 0 | 0 |
T12 | 60921 | 29680 | 0 | 0 |
T19 | 993 | 23 | 0 | 0 |
T20 | 483588 | 456947 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 659 | 659 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 434955930 | 140111750 | 0 | 0 |
DepthKnown_A | 434955930 | 434851178 | 0 | 0 |
RvalidKnown_A | 434955930 | 434851178 | 0 | 0 |
WreadyKnown_A | 434955930 | 434851178 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 659 | 659 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 140111750 | 0 | 0 |
T1 | 20341 | 7716 | 0 | 0 |
T2 | 1122 | 21 | 0 | 0 |
T3 | 156132 | 76709 | 0 | 0 |
T4 | 524028 | 258219 | 0 | 0 |
T5 | 53897 | 25615 | 0 | 0 |
T7 | 75074 | 36787 | 0 | 0 |
T8 | 17724 | 6899 | 0 | 0 |
T12 | 60921 | 29680 | 0 | 0 |
T19 | 993 | 120 | 0 | 0 |
T20 | 483588 | 205847 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 659 | 659 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 434955930 | 23543595 | 0 | 0 |
DepthKnown_A | 434955930 | 434851178 | 0 | 0 |
RvalidKnown_A | 434955930 | 434851178 | 0 | 0 |
WreadyKnown_A | 434955930 | 434851178 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 659 | 659 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 23543595 | 0 | 0 |
T1 | 20341 | 1217 | 0 | 0 |
T2 | 1122 | 0 | 0 | 0 |
T3 | 156132 | 18854 | 0 | 0 |
T4 | 524028 | 63375 | 0 | 0 |
T5 | 53897 | 9387 | 0 | 0 |
T6 | 0 | 32874 | 0 | 0 |
T7 | 75074 | 9092 | 0 | 0 |
T8 | 17724 | 224 | 0 | 0 |
T12 | 60921 | 7181 | 0 | 0 |
T19 | 993 | 0 | 0 | 0 |
T20 | 483588 | 115607 | 0 | 0 |
T24 | 0 | 3360 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 659 | 659 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 434955930 | 33493933 | 0 | 0 |
DepthKnown_A | 434955930 | 434851178 | 0 | 0 |
RvalidKnown_A | 434955930 | 434851178 | 0 | 0 |
WreadyKnown_A | 434955930 | 434851178 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 659 | 659 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 33493933 | 0 | 0 |
T1 | 20341 | 1217 | 0 | 0 |
T2 | 1122 | 0 | 0 | 0 |
T3 | 156132 | 18854 | 0 | 0 |
T4 | 524028 | 63375 | 0 | 0 |
T5 | 53897 | 9387 | 0 | 0 |
T6 | 0 | 32874 | 0 | 0 |
T7 | 75074 | 9092 | 0 | 0 |
T8 | 17724 | 1002 | 0 | 0 |
T12 | 60921 | 7181 | 0 | 0 |
T19 | 993 | 0 | 0 | 0 |
T20 | 483588 | 522512 | 0 | 0 |
T24 | 0 | 15290 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 659 | 659 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 434955930 | 69531755 | 0 | 0 |
DepthKnown_A | 434955930 | 434851178 | 0 | 0 |
RvalidKnown_A | 434955930 | 434851178 | 0 | 0 |
WreadyKnown_A | 434955930 | 434851178 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 659 | 659 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 69531755 | 0 | 0 |
T1 | 20341 | 6499 | 0 | 0 |
T2 | 1122 | 21 | 0 | 0 |
T3 | 156132 | 57855 | 0 | 0 |
T4 | 524028 | 194844 | 0 | 0 |
T5 | 53897 | 16228 | 0 | 0 |
T7 | 75074 | 27695 | 0 | 0 |
T8 | 17724 | 1300 | 0 | 0 |
T12 | 60921 | 22499 | 0 | 0 |
T19 | 993 | 23 | 0 | 0 |
T20 | 483588 | 341340 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 659 | 659 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
44 | 1 | 1 | |
45 | 1 | 1 | |
48 | 1 | 1 | |
49 | 1 | 1 | |
53 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 5 | 5 | 100.00 | 5 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 5 | 5 | 100.00 | 5 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataKnown_A | 434955930 | 106617817 | 0 | 0 |
DepthKnown_A | 434955930 | 434851178 | 0 | 0 |
RvalidKnown_A | 434955930 | 434851178 | 0 | 0 |
WreadyKnown_A | 434955930 | 434851178 | 0 | 0 |
gen_passthru_fifo.paramCheckPass | 659 | 659 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 106617817 | 0 | 0 |
T1 | 20341 | 6499 | 0 | 0 |
T2 | 1122 | 21 | 0 | 0 |
T3 | 156132 | 57855 | 0 | 0 |
T4 | 524028 | 194844 | 0 | 0 |
T5 | 53897 | 16228 | 0 | 0 |
T7 | 75074 | 27695 | 0 | 0 |
T8 | 17724 | 5897 | 0 | 0 |
T12 | 60921 | 22499 | 0 | 0 |
T19 | 993 | 120 | 0 | 0 |
T20 | 483588 | 153596 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434955930 | 434851178 | 0 | 0 |
T1 | 20341 | 20285 | 0 | 0 |
T2 | 1122 | 1046 | 0 | 0 |
T3 | 156132 | 156071 | 0 | 0 |
T4 | 524028 | 523964 | 0 | 0 |
T5 | 53897 | 53847 | 0 | 0 |
T7 | 75074 | 74981 | 0 | 0 |
T8 | 17724 | 17648 | 0 | 0 |
T12 | 60921 | 60857 | 0 | 0 |
T19 | 993 | 919 | 0 | 0 |
T20 | 483588 | 483549 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 659 | 659 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |