Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 44553156 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 42242811 1 T1 4901 T2 621 T3 936946



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 41312216 1 T1 4852 T2 604 T3 893151
values[0x0] 21308673 1 T1 2125 T2 267 T3 486445
values[0x1] 24175078 1 T1 2441 T2 306 T3 535155



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 34285276 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 52510691 1 T1 5966 T2 778 T3 115752



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 277412 1 T1 24 T3 7010 T7 78
valid_sources[0x01] 334959 1 T1 26 T3 7168 T7 35
valid_sources[0x02] 318162 1 T1 37 T3 7779 T7 81
valid_sources[0x03] 305501 1 T1 45 T3 7468 T7 79
valid_sources[0x04] 286056 1 T1 51 T3 7094 T7 61
valid_sources[0x05] 390151 1 T1 29 T3 7069 T7 61
valid_sources[0x06] 278533 1 T1 37 T3 7963 T7 51
valid_sources[0x07] 286401 1 T1 42 T3 7352 T7 59
valid_sources[0x08] 304001 1 T1 32 T3 7407 T7 44
valid_sources[0x09] 330785 1 T1 45 T3 7162 T7 39
valid_sources[0x0a] 275416 1 T1 43 T3 7138 T7 39
valid_sources[0x0b] 305255 1 T1 38 T3 8122 T7 49
valid_sources[0x0c] 282043 1 T1 43 T3 7287 T7 22
valid_sources[0x0d] 372774 1 T1 36 T3 7609 T7 66
valid_sources[0x0e] 367333 1 T1 29 T3 7715 T7 50
valid_sources[0x0f] 281373 1 T1 35 T3 7170 T7 42
valid_sources[0x10] 278961 1 T1 36 T3 7684 T7 72
valid_sources[0x11] 281210 1 T1 29 T3 7589 T7 54
valid_sources[0x12] 295252 1 T1 51 T3 8073 T7 42
valid_sources[0x13] 277269 1 T1 48 T3 6936 T7 49
valid_sources[0x14] 369356 1 T1 52 T3 7019 T7 56
valid_sources[0x15] 287733 1 T1 43 T3 7572 T7 64
valid_sources[0x16] 282442 1 T1 39 T3 7611 T7 73
valid_sources[0x17] 342792 1 T1 44 T3 7718 T7 46
valid_sources[0x18] 283878 1 T1 38 T3 7411 T7 61
valid_sources[0x19] 278677 1 T1 49 T3 7741 T7 76
valid_sources[0x1a] 332674 1 T1 33 T3 8191 T7 53
valid_sources[0x1b] 280336 1 T1 44 T3 8043 T7 50
valid_sources[0x1c] 280048 1 T1 32 T3 8083 T7 34
valid_sources[0x1d] 282867 1 T1 25 T3 7259 T7 50
valid_sources[0x1e] 321663 1 T1 25 T3 7635 T7 58
valid_sources[0x1f] 285752 1 T1 59 T3 7385 T7 39
valid_sources[0x20] 335291 1 T1 33 T3 7368 T7 48
valid_sources[0x21] 278243 1 T1 35 T3 7262 T7 33
valid_sources[0x22] 278554 1 T1 42 T3 7434 T7 70
valid_sources[0x23] 279728 1 T1 36 T3 6971 T7 44
valid_sources[0x24] 330530 1 T1 25 T3 7463 T7 65
valid_sources[0x25] 280734 1 T1 47 T3 8632 T7 57
valid_sources[0x26] 321357 1 T1 58 T3 7581 T7 49
valid_sources[0x27] 425653 1 T1 30 T3 7701 T7 83
valid_sources[0x28] 286750 1 T1 40 T3 7467 T7 41
valid_sources[0x29] 279180 1 T1 38 T3 7549 T7 67
valid_sources[0x2a] 280433 1 T1 33 T3 7518 T7 38
valid_sources[0x2b] 320950 1 T1 26 T3 6910 T7 54
valid_sources[0x2c] 806756 1 T1 39 T3 7191 T7 48
valid_sources[0x2d] 281126 1 T1 46 T3 7108 T7 48
valid_sources[0x2e] 379159 1 T1 44 T3 7966 T7 47
valid_sources[0x2f] 280703 1 T1 28 T3 7701 T7 48
valid_sources[0x30] 387389 1 T1 39 T3 7562 T7 64
valid_sources[0x31] 281626 1 T1 26 T3 7824 T7 61
valid_sources[0x32] 279375 1 T1 26 T3 7483 T7 54
valid_sources[0x33] 282866 1 T1 29 T3 7593 T7 54
valid_sources[0x34] 347592 1 T1 40 T3 7592 T7 69
valid_sources[0x35] 344118 1 T1 32 T3 7542 T7 45
valid_sources[0x36] 285782 1 T1 42 T3 7485 T7 63
valid_sources[0x37] 283102 1 T1 32 T3 6936 T7 50
valid_sources[0x38] 305214 1 T1 52 T3 8034 T7 54
valid_sources[0x39] 284959 1 T1 20 T3 7626 T7 58
valid_sources[0x3a] 285714 1 T1 27 T3 7598 T7 56
valid_sources[0x3b] 277104 1 T1 29 T3 7304 T7 31
valid_sources[0x3c] 282829 1 T1 42 T3 7558 T7 75
valid_sources[0x3d] 300723 1 T1 51 T3 7666 T7 43
valid_sources[0x3e] 1137094 1 T1 45 T3 6840 T7 89
valid_sources[0x3f] 374455 1 T1 42 T3 7169 T7 67
valid_sources[0x40] 735470 1 T1 39 T3 7321 T7 59
valid_sources[0x41] 280980 1 T1 29 T3 7804 T7 35
valid_sources[0x42] 282915 1 T1 49 T3 7460 T7 43
valid_sources[0x43] 279865 1 T1 36 T3 7468 T7 38
valid_sources[0x44] 281454 1 T1 38 T3 7584 T7 51
valid_sources[0x45] 412697 1 T1 44 T3 7246 T7 56
valid_sources[0x46] 441138 1 T1 35 T3 7539 T7 48
valid_sources[0x47] 280838 1 T1 49 T3 7672 T7 80
valid_sources[0x48] 283540 1 T1 32 T3 7554 T7 59
valid_sources[0x49] 302284 1 T1 36 T3 7347 T7 55
valid_sources[0x4a] 498116 1 T1 36 T3 7707 T7 48
valid_sources[0x4b] 283741 1 T1 24 T3 7838 T7 56
valid_sources[0x4c] 277809 1 T1 46 T3 7198 T7 32
valid_sources[0x4d] 280859 1 T1 30 T3 7438 T7 55
valid_sources[0x4e] 338221 1 T1 25 T3 8001 T7 72
valid_sources[0x4f] 284332 1 T1 26 T3 7215 T7 43
valid_sources[0x50] 276750 1 T1 32 T3 7377 T7 35
valid_sources[0x51] 281602 1 T1 31 T3 7846 T7 53
valid_sources[0x52] 286224 1 T1 50 T3 7679 T7 46
valid_sources[0x53] 278239 1 T1 34 T3 7343 T7 46
valid_sources[0x54] 480383 1 T1 49 T3 7769 T7 41
valid_sources[0x55] 283331 1 T1 43 T3 6653 T7 59
valid_sources[0x56] 283678 1 T1 28 T3 7369 T7 70
valid_sources[0x57] 390641 1 T1 38 T3 7171 T7 33
valid_sources[0x58] 309944 1 T1 30 T3 7549 T7 38
valid_sources[0x59] 279507 1 T1 43 T3 8066 T7 22
valid_sources[0x5a] 277664 1 T1 43 T3 6555 T7 37
valid_sources[0x5b] 276921 1 T1 50 T3 7032 T7 32
valid_sources[0x5c] 279017 1 T1 42 T3 7601 T7 50
valid_sources[0x5d] 303443 1 T1 57 T3 7906 T7 62
valid_sources[0x5e] 289306 1 T1 26 T3 7389 T7 62
valid_sources[0x5f] 289173 1 T1 37 T3 7136 T7 70
valid_sources[0x60] 463029 1 T1 34 T3 7566 T7 33
valid_sources[0x61] 277583 1 T1 37 T3 8043 T7 38
valid_sources[0x62] 290063 1 T1 37 T3 7426 T7 83
valid_sources[0x63] 384537 1 T1 49 T3 7757 T7 51
valid_sources[0x64] 311437 1 T1 45 T3 7066 T7 95
valid_sources[0x65] 330041 1 T1 35 T3 8003 T7 44
valid_sources[0x66] 346880 1 T1 29 T3 7486 T14 1
valid_sources[0x67] 278105 1 T1 32 T3 6967 T7 51
valid_sources[0x68] 282337 1 T1 36 T3 6899 T7 44
valid_sources[0x69] 280433 1 T1 31 T3 7873 T7 42
valid_sources[0x6a] 285262 1 T1 51 T3 6684 T7 34
valid_sources[0x6b] 278868 1 T1 34 T3 8108 T7 61
valid_sources[0x6c] 278449 1 T1 35 T3 7293 T7 61
valid_sources[0x6d] 324670 1 T1 45 T3 7904 T7 54
valid_sources[0x6e] 279661 1 T1 32 T3 7201 T7 54
valid_sources[0x6f] 279229 1 T1 36 T3 7397 T7 53
valid_sources[0x70] 319340 1 T1 31 T3 8053 T7 31
valid_sources[0x71] 280214 1 T1 31 T3 7847 T7 62
valid_sources[0x72] 282279 1 T1 37 T3 7130 T7 46
valid_sources[0x73] 2301968 1 T1 29 T3 7291 T7 75
valid_sources[0x74] 282327 1 T1 48 T3 7106 T7 41
valid_sources[0x75] 280851 1 T1 50 T3 7648 T7 71
valid_sources[0x76] 299598 1 T1 46 T3 7521 T7 56
valid_sources[0x77] 276698 1 T1 39 T3 6947 T7 49
valid_sources[0x78] 279690 1 T1 39 T3 7261 T7 53
valid_sources[0x79] 276214 1 T1 28 T3 6721 T7 61
valid_sources[0x7a] 279722 1 T1 31 T3 7280 T7 56
valid_sources[0x7b] 289594 1 T1 37 T3 7319 T7 60
valid_sources[0x7c] 279717 1 T1 38 T3 7821 T7 47
valid_sources[0x7d] 279170 1 T1 39 T3 7388 T7 56
valid_sources[0x7e] 283623 1 T1 29 T3 7905 T7 59
valid_sources[0x7f] 282854 1 T1 30 T3 8246 T7 51
valid_sources[0x80] 285111 1 T1 48 T3 7481 T7 21



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 20391443 1 T1 2404 T2 293 T3 446678
values[0x0] all_enables biggest_size 11765253 1 T1 1276 T2 175 T3 265910
values[0x1] all_enables biggest_size 10086115 1 T1 1221 T2 153 T3 224358

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%