Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

47535506

1

T1

4517

T2

556

T3

977805

full_word

42436676

1

T1

4901

T2

621

T3

936946

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	89971792	1			T1	9418		T2	1177		T3	191475
auto[TlIntgErrCmd]	129	1			T49	8		T50	6		T51	5
auto[TlIntgErrData]	137	1			T49	12		T50	17		T51	7
auto[TlIntgErrBoth]	124	1			T49	10		T50	7		T51	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42313345

1

T1

4852

T2

604

T3

893151

auto[1]

47658837

1

T1

4566

T2

573

T3

102160

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21845033	1			T1	2448		T2	311		T3	446473
auto[TlIntgErrNone]	partial	auto[1]	25690116	1			T1	2069		T2	245		T3	531332
auto[TlIntgErrNone]	full_word	auto[0]	20468152	1			T1	2404		T2	293		T3	446678
auto[TlIntgErrNone]	full_word	auto[1]	21968491	1			T1	2497		T2	328		T3	490268
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T49	3		T50	1		T51	3
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T49	5		T50	5		T51	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T130	1		T132	1		T133	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T134	1		T135	1		T131	2
auto[TlIntgErrData]	partial	auto[0]	55	1			T49	7		T50	9		T51	4
auto[TlIntgErrData]	partial	auto[1]	71	1			T49	5		T50	7		T51	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T134	1		T135	1		T136	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T50	1		T51	1		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T49	3		T50	2		T51	2
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T49	5		T50	5		T51	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T49	1		T132	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T49	1		T51	1		T138	1