Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	490044059	1708193	0	0
intr_enable_rd_A	490044059	2689	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490044059	1708193	0	0
T9	223639	76517	0	0
T10	0	82865	0	0
T11	0	208723	0	0
T13	0	106284	0	0
T21	0	435693	0	0
T22	0	332479	0	0
T23	0	292654	0	0
T52	0	66600	0	0
T53	0	8	0	0
T54	0	505	0	0
T55	1039	0	0	0
T56	340529	0	0	0
T57	104849	0	0	0
T58	1136	0	0	0
T59	15412	0	0	0
T60	709481	0	0	0
T61	652266	0	0	0
T62	155014	0	0	0
T63	1879	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490044059	2689	0	0
T10	0	105	0	0
T20	742078	30	0	0
T39	19254	0	0	0
T40	120209	0	0	0
T42	308281	0	0	0
T64	0	25	0	0
T65	0	26	0	0
T66	0	48	0	0
T67	0	33	0	0
T68	0	37	0	0
T69	0	92	0	0
T70	0	26	0	0
T71	0	43	0	0
T72	98613	0	0	0
T73	504242	0	0	0
T74	79815	0	0	0
T75	26403	0	0	0
T76	21847	0	0	0
T77	96141	0	0	0