Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42291014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40333338

1

T1

10466

T2

2

T3

18231

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39276055	1			T1	7074		T2	1		T3	18849
values[0x0]	20329180	1			T1	4993		T2	2		T3	8940
values[0x1]	23019117	1			T1	5185		T2	2		T3	10147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32568627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50055725

1

T1

11711

T2

2

T3

22694

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	257725	1			T1	85		T3	136		T5	305
valid_sources[0x01]	294087	1			T1	66		T2	5		T3	116
valid_sources[0x02]	289732	1			T1	68		T3	161		T5	339
valid_sources[0x03]	261281	1			T1	66		T3	171		T5	310
valid_sources[0x04]	731562	1			T1	65		T3	171		T5	306
valid_sources[0x05]	262901	1			T1	74		T3	171		T5	260
valid_sources[0x06]	267430	1			T1	55		T3	155		T5	315
valid_sources[0x07]	274309	1			T1	70		T3	153		T5	399
valid_sources[0x08]	268234	1			T1	63		T3	134		T5	361
valid_sources[0x09]	264521	1			T1	73		T3	153		T5	347
valid_sources[0x0a]	271258	1			T1	73		T3	143		T5	416
valid_sources[0x0b]	261656	1			T1	73		T3	162		T5	239
valid_sources[0x0c]	267928	1			T1	65		T3	131		T5	327
valid_sources[0x0d]	267731	1			T1	78		T3	146		T4	1
valid_sources[0x0e]	262328	1			T1	66		T3	151		T5	420
valid_sources[0x0f]	261482	1			T1	64		T3	150		T5	288
valid_sources[0x10]	1406634	1			T1	77		T3	138		T5	266
valid_sources[0x11]	290652	1			T1	62		T3	145		T5	441
valid_sources[0x12]	262909	1			T1	74		T3	153		T5	408
valid_sources[0x13]	779536	1			T1	70		T3	128		T5	278
valid_sources[0x14]	259889	1			T1	87		T3	130		T5	327
valid_sources[0x15]	259434	1			T1	56		T3	142		T5	227
valid_sources[0x16]	267269	1			T1	62		T3	164		T5	401
valid_sources[0x17]	275766	1			T1	66		T3	116		T5	411
valid_sources[0x18]	322458	1			T1	64		T3	161		T5	301
valid_sources[0x19]	265898	1			T1	53		T3	162		T5	344
valid_sources[0x1a]	259827	1			T1	68		T3	159		T5	317
valid_sources[0x1b]	273640	1			T1	66		T3	119		T5	237
valid_sources[0x1c]	334662	1			T1	73		T3	165		T5	373
valid_sources[0x1d]	1298349	1			T1	71		T3	154		T5	321
valid_sources[0x1e]	271140	1			T1	62		T3	148		T5	279
valid_sources[0x1f]	262137	1			T1	59		T3	157		T5	364
valid_sources[0x20]	266848	1			T1	80		T3	142		T5	452
valid_sources[0x21]	271796	1			T1	65		T3	167		T5	283
valid_sources[0x22]	271958	1			T1	47		T3	166		T5	226
valid_sources[0x23]	344734	1			T1	59		T3	138		T5	326
valid_sources[0x24]	266601	1			T1	68		T3	122		T5	381
valid_sources[0x25]	542262	1			T1	67		T3	121		T5	287
valid_sources[0x26]	283530	1			T1	64		T3	140		T4	1
valid_sources[0x27]	262885	1			T1	79		T3	154		T5	345
valid_sources[0x28]	262969	1			T1	61		T3	131		T5	224
valid_sources[0x29]	264991	1			T1	59		T3	135		T5	378
valid_sources[0x2a]	340397	1			T1	67		T3	152		T5	324
valid_sources[0x2b]	460042	1			T1	61		T3	156		T4	167183
valid_sources[0x2c]	271652	1			T1	64		T3	150		T5	365
valid_sources[0x2d]	264298	1			T1	50		T3	171		T5	281
valid_sources[0x2e]	261761	1			T1	86		T3	177		T5	229
valid_sources[0x2f]	375427	1			T1	82		T3	185		T5	334
valid_sources[0x30]	272805	1			T1	62		T3	136		T5	366
valid_sources[0x31]	377821	1			T1	69		T3	129		T5	416
valid_sources[0x32]	350580	1			T1	70		T3	149		T5	266
valid_sources[0x33]	267879	1			T1	59		T3	125		T5	345
valid_sources[0x34]	333648	1			T1	73		T3	136		T5	328
valid_sources[0x35]	282114	1			T1	64		T3	131		T5	394
valid_sources[0x36]	284703	1			T1	63		T3	100		T5	386
valid_sources[0x37]	257273	1			T1	62		T3	162		T5	307
valid_sources[0x38]	262425	1			T1	55		T3	140		T5	291
valid_sources[0x39]	261644	1			T1	62		T3	158		T5	421
valid_sources[0x3a]	270999	1			T1	62		T3	161		T5	237
valid_sources[0x3b]	263073	1			T1	75		T3	154		T5	301
valid_sources[0x3c]	273254	1			T1	57		T3	137		T5	359
valid_sources[0x3d]	296386	1			T1	68		T3	150		T5	346
valid_sources[0x3e]	263441	1			T1	63		T3	128		T4	1
valid_sources[0x3f]	402081	1			T1	81		T3	140		T5	360
valid_sources[0x40]	268168	1			T1	59		T3	161		T5	453
valid_sources[0x41]	427767	1			T1	71		T3	162		T5	267
valid_sources[0x42]	266749	1			T1	71		T3	115		T5	356
valid_sources[0x43]	358900	1			T1	100		T3	147		T4	85572
valid_sources[0x44]	271318	1			T1	75		T3	161		T5	306
valid_sources[0x45]	255199	1			T1	48		T3	143		T5	257
valid_sources[0x46]	564672	1			T1	59		T3	121		T5	322
valid_sources[0x47]	277959	1			T1	68		T3	170		T5	374
valid_sources[0x48]	276873	1			T1	62		T3	153		T5	427
valid_sources[0x49]	269138	1			T1	48		T3	191		T5	414
valid_sources[0x4a]	260513	1			T1	51		T3	157		T5	340
valid_sources[0x4b]	277936	1			T1	71		T3	156		T5	269
valid_sources[0x4c]	424696	1			T1	71		T3	168		T5	416
valid_sources[0x4d]	262827	1			T1	68		T3	166		T5	394
valid_sources[0x4e]	266518	1			T1	78		T3	156		T5	327
valid_sources[0x4f]	552115	1			T1	55		T3	142		T5	411
valid_sources[0x50]	272239	1			T1	70		T3	184		T5	305
valid_sources[0x51]	297929	1			T1	99		T3	129		T5	288
valid_sources[0x52]	263879	1			T1	62		T3	133		T5	328
valid_sources[0x53]	264117	1			T1	65		T3	188		T5	453
valid_sources[0x54]	274508	1			T1	51		T3	145		T5	358
valid_sources[0x55]	259686	1			T1	50		T3	153		T5	327
valid_sources[0x56]	445611	1			T1	71		T3	134		T5	321
valid_sources[0x57]	292697	1			T1	79		T3	157		T5	440
valid_sources[0x58]	266094	1			T1	73		T3	120		T5	267
valid_sources[0x59]	345864	1			T1	71		T3	135		T5	351
valid_sources[0x5a]	736082	1			T1	53		T3	163		T5	368
valid_sources[0x5b]	262048	1			T1	92		T3	151		T5	327
valid_sources[0x5c]	264716	1			T1	74		T3	168		T5	374
valid_sources[0x5d]	269161	1			T1	76		T3	106		T5	253
valid_sources[0x5e]	295209	1			T1	63		T3	147		T5	383
valid_sources[0x5f]	262664	1			T1	56		T3	165		T5	330
valid_sources[0x60]	673257	1			T1	80		T3	171		T5	407
valid_sources[0x61]	263987	1			T1	69		T3	136		T5	318
valid_sources[0x62]	325272	1			T1	68		T3	146		T5	346
valid_sources[0x63]	263809	1			T1	65		T3	131		T5	282
valid_sources[0x64]	268927	1			T1	61		T3	140		T5	321
valid_sources[0x65]	270832	1			T1	57		T3	139		T5	303
valid_sources[0x66]	262373	1			T1	62		T3	140		T5	289
valid_sources[0x67]	317663	1			T1	59		T3	128		T5	294
valid_sources[0x68]	257643	1			T1	64		T3	103		T5	176
valid_sources[0x69]	266058	1			T1	72		T3	162		T5	332
valid_sources[0x6a]	284316	1			T1	68		T3	141		T5	501
valid_sources[0x6b]	266286	1			T1	58		T3	145		T5	477
valid_sources[0x6c]	270370	1			T1	65		T3	145		T5	248
valid_sources[0x6d]	260526	1			T1	58		T3	135		T5	355
valid_sources[0x6e]	283134	1			T1	78		T3	162		T5	388
valid_sources[0x6f]	262961	1			T1	47		T3	155		T5	352
valid_sources[0x70]	307722	1			T1	60		T3	143		T5	349
valid_sources[0x71]	271586	1			T1	50		T3	156		T5	265
valid_sources[0x72]	261274	1			T1	64		T3	152		T5	488
valid_sources[0x73]	263440	1			T1	60		T3	151		T4	1
valid_sources[0x74]	259339	1			T1	70		T3	123		T5	343
valid_sources[0x75]	282133	1			T1	64		T3	116		T5	289
valid_sources[0x76]	267346	1			T1	75		T3	151		T5	364
valid_sources[0x77]	267352	1			T1	84		T3	136		T5	352
valid_sources[0x78]	387800	1			T1	64		T3	151		T5	287
valid_sources[0x79]	336148	1			T1	65		T3	140		T4	28800
valid_sources[0x7a]	424199	1			T1	77		T3	154		T5	309
valid_sources[0x7b]	260968	1			T1	71		T3	154		T5	291
valid_sources[0x7c]	428123	1			T1	75		T3	157		T5	348
valid_sources[0x7d]	324743	1			T1	64		T3	147		T5	480
valid_sources[0x7e]	509809	1			T1	75		T3	182		T5	343
valid_sources[0x7f]	268118	1			T1	80		T3	149		T5	394
valid_sources[0x80]	321108	1			T1	71		T3	179		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19405824

1

T1

3500

T2

1

T3

9282

values[0x0]

all_enables

biggest_size

11262710

1

T1

3606

T2

1

T3

4822

values[0x1]

all_enables

biggest_size

9664804

1

T1

3360

T3

4127

T4

41553