SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[hmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 64985951 | 1 | T1 | 10727 | T2 | 5 | T3 | 30783 | ||||
auto[1] | 20485739 | 1 | T1 | 6525 | T3 | 7153 | T4 | 94024 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 85471416 | 1 | T1 | 17252 | T2 | 5 | T3 | 37936 | ||||
values[1] | 23 | 1 | T63 | 2 | T65 | 2 | T128 | 2 | ||||
values[2] | 6 | 1 | T64 | 2 | T65 | 1 | T129 | 1 | ||||
values[3] | 155 | 1 | T63 | 18 | T64 | 3 | T65 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 85471438 | 1 | T1 | 17252 | T2 | 5 | T3 | 37936 | ||||
values[1] | 26 | 1 | T63 | 1 | T65 | 1 | T128 | 5 | ||||
values[2] | 9 | 1 | T63 | 1 | T130 | 1 | T131 | 1 | ||||
values[3] | 132 | 1 | T63 | 7 | T64 | 3 | T65 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 85471300 | 1 | T1 | 17252 | T2 | 5 | T3 | 37936 | ||||
auto[TlIntgErrCmd] | 138 | 1 | T63 | 18 | T64 | 5 | T65 | 14 | ||||
auto[TlIntgErrData] | 116 | 1 | T63 | 2 | T64 | 3 | T65 | 10 | ||||
auto[TlIntgErrBoth] | 136 | 1 | T63 | 10 | T64 | 2 | T65 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |