Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44965415

1

T1

6786

T2

3

T3

19705

full_word

40506275

1

T1

10466

T2

2

T3

18231

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	85471300	1			T1	17252		T2	5		T3	37936
auto[TlIntgErrCmd]	138	1			T63	18		T64	5		T65	14
auto[TlIntgErrData]	116	1			T63	2		T64	3		T65	10
auto[TlIntgErrBoth]	136	1			T63	10		T64	2		T65	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40173871

1

T1

7074

T2

1

T3

18849

auto[1]

45297819

1

T1

10178

T2

4

T3

19087

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20699797	1			T1	3574		T3	9567		T4	82280
auto[TlIntgErrNone]	partial	auto[1]	24265267	1			T1	3212		T2	3		T3	10138
auto[TlIntgErrNone]	full_word	auto[0]	19473898	1			T1	3500		T2	1		T3	9282
auto[TlIntgErrNone]	full_word	auto[1]	21032338	1			T1	6966		T2	1		T3	8949
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T63	7		T64	3		T65	4
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T63	9		T64	1		T65	9
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T63	2		T64	1		T65	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T129	1		T132	1		T133	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T64	1		T65	4		T128	5
auto[TlIntgErrData]	partial	auto[1]	52	1			T63	2		T64	1		T65	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T132	2		T134	1		T135	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T64	1		T65	2		T128	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T63	4		T64	2		T65	2
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T63	4		T65	3		T128	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T129	1		T136	1		T135	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T63	2		T65	1		T128	1