Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	445307016	1540890	0	0
intr_enable_rd_A	445307016	2643	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445307016	1540890	0	0
T7	56395	0	0	0
T10	953668	155084	0	0
T11	0	91188	0	0
T12	0	55940	0	0
T13	174820	28537	0	0
T67	0	194448	0	0
T68	0	165851	0	0
T69	0	103047	0	0
T70	0	199378	0	0
T71	0	45883	0	0
T72	0	28207	0	0
T73	22220	0	0	0
T74	133503	0	0	0
T75	104315	0	0	0
T76	483208	0	0	0
T77	260923	0	0	0
T78	209528	0	0	0
T79	31504	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445307016	2643	0	0
T10	0	291	0	0
T13	0	47	0	0
T49	422832	7	0	0
T80	0	36	0	0
T81	0	55	0	0
T82	0	6	0	0
T83	0	61	0	0
T84	0	10	0	0
T85	0	24	0	0
T86	0	9	0	0
T87	10369	0	0	0
T88	22731	0	0	0
T89	39831	0	0	0
T90	154124	0	0	0
T91	266382	0	0	0
T92	1378	0	0	0
T93	260025	0	0	0
T94	134745	0	0	0
T95	209811	0	0	0