Module Definition
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Module Instance : tb.dut.u_tlul_adapter.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.64 92.86 100.00 85.71 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.20 97.14 100.00 91.67 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.80 98.57 100.00 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.43 85.71 100.00 100.00 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.57 94.29 100.00 100.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.80 98.57 100.00 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_msg_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.71 100.00 93.33 100.00 100.00 98.90 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_adapter.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.80 98.57 100.00 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_msg_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
86.43 85.71
tb.dut.u_tlul_adapter.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL151280.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
84.64 92.86
tb.dut.u_tlul_adapter.u_rspfifo

Line No.TotalCoveredPercent
TOTAL151386.67
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
86.43 100.00
tb.dut.u_tlul_adapter.u_sramreqfifo

TotalCoveredPercent
Conditions16531.25
Logical16531.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_msg_fifo

TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT14,T8,T20
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT14,T15,T16
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
84.64 100.00
tb.dut.u_tlul_adapter.u_rspfifo

TotalCoveredPercent
Conditions24833.33
Logical24833.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T4,T6
110Not Covered
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_msg_fifo

SCOREBRANCH
84.64 85.71
tb.dut.u_tlul_adapter.u_rspfifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

SCOREBRANCH
86.43 100.00
tb.dut.u_tlul_adapter.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 517241531 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1719933580 55613404 0 0
gen_passthru_fifo.paramCheckPass 3960 3960 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 517241531 0 0
T1 292720 87907 0 0
T2 5856 20 0 0
T3 2184104 163066 0 0
T4 2793416 1877417 0 0
T5 1441424 458720 0 0
T6 2413960 1981568 0 0
T9 2270720 629242 0 0
T17 2137928 584135 0 0
T18 448808 93225 0 0
T19 1551032 411905 0 0
T21 0 13233 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 365900 365180 0 0
T2 7320 6730 0 0
T3 2730130 2728650 0 0
T4 3491770 3491100 0 0
T5 1801780 1800950 0 0
T6 3017450 3017300 0 0
T9 2838400 2837900 0 0
T17 2672410 2671610 0 0
T18 561010 560420 0 0
T19 1938790 1938140 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 365900 365180 0 0
T2 7320 6730 0 0
T3 2730130 2728650 0 0
T4 3491770 3491100 0 0
T5 1801780 1800950 0 0
T6 3017450 3017300 0 0
T9 2838400 2837900 0 0
T17 2672410 2671610 0 0
T18 561010 560420 0 0
T19 1938790 1938140 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 365900 365180 0 0
T2 7320 6730 0 0
T3 2730130 2728650 0 0
T4 3491770 3491100 0 0
T5 1801780 1800950 0 0
T6 3017450 3017300 0 0
T9 2838400 2837900 0 0
T17 2672410 2671610 0 0
T18 561010 560420 0 0
T19 1938790 1938140 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1719933580 55613404 0 0
T1 73180 18899 0 0
T2 1464 0 0 0
T3 546026 11322 0 0
T4 698354 542104 0 0
T5 360356 112112 0 0
T6 603490 275214 0 0
T9 567680 73654 0 0
T17 534482 58259 0 0
T18 112202 10653 0 0
T19 387758 32013 0 0
T21 0 7017 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 3960 3960 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T6 6 6 0 0
T9 6 6 0 0
T17 6 6 0 0
T18 6 6 0 0
T19 6 6 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Line No.TotalCoveredPercent
TOTAL141392.86
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11Excluded VC_COV_UNR

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 130 1 1 100.00
TERNARY 138 1 1 100.00
IF 69 3 3 100.00
IF 123 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded VC_COV_UNR


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 429983395 0 0 0
DepthKnown_A 429983395 429919609 0 0
RvalidKnown_A 429983395 429919609 0 0
WreadyKnown_A 429983395 429919609 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 429983395 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 0 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL141285.71
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 138 1 1 100.00
IF 69 3 3 100.00
IF 111 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded VC_COV_UNR


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 429983395 0 0 0
DepthKnown_A 429983395 429919609 0 0
RvalidKnown_A 429983395 429919609 0 0
WreadyKnown_A 429983395 429919609 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 429983395 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 0 0 0

Line Coverage for Instance : tb.dut.u_msg_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_msg_fifo
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT14,T8,T20
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101CoveredT14,T15,T16
110Excluded VC_COV_UNR
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T3,T4
110Excluded VC_COV_UNR
111CoveredT1,T3,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_msg_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_msg_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 429983395 23040143 0 0
DepthKnown_A 429983395 429919609 0 0
RvalidKnown_A 429983395 429919609 0 0
WreadyKnown_A 429983395 429919609 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 429983395 23040143 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 23040143 0 0
T1 36590 12374 0 0
T2 732 0 0 0
T3 273013 4169 0 0
T4 349177 119365 0 0
T5 180178 79241 0 0
T6 301745 158150 0 0
T9 283840 39598 0 0
T17 267241 31927 0 0
T18 56101 5661 0 0
T19 193879 8910 0 0
T21 0 1952 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 23040143 0 0
T1 36590 12374 0 0
T2 732 0 0 0
T3 273013 4169 0 0
T4 349177 119365 0 0
T5 180178 79241 0 0
T6 301745 158150 0 0
T9 283840 39598 0 0
T17 267241 31927 0 0
T18 56101 5661 0 0
T19 193879 8910 0 0
T21 0 1952 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT3,T4,T6
110Excluded VC_COV_UNR
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 429983395 32573261 0 0
DepthKnown_A 429983395 429919609 0 0
RvalidKnown_A 429983395 429919609 0 0
WreadyKnown_A 429983395 429919609 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 429983395 32573261 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 32573261 0 0
T1 36590 6525 0 0
T2 732 0 0 0
T3 273013 7153 0 0
T4 349177 422739 0 0
T5 180178 32871 0 0
T6 301745 117064 0 0
T9 283840 34056 0 0
T17 267241 26332 0 0
T18 56101 4992 0 0
T19 193879 23103 0 0
T21 0 5065 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 429919609 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 429983395 32573261 0 0
T1 36590 6525 0 0
T2 732 0 0 0
T3 273013 7153 0 0
T4 349177 422739 0 0
T5 180178 32871 0 0
T6 301745 117064 0 0
T9 283840 34056 0 0
T17 267241 26332 0 0
T18 56101 4992 0 0
T19 193879 23103 0 0
T21 0 5065 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 445307016 92874465 0 0
DepthKnown_A 445307016 445199589 0 0
RvalidKnown_A 445307016 445199589 0 0
WreadyKnown_A 445307016 445199589 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 92874465 0 0
T1 36590 17252 0 0
T2 732 5 0 0
T3 273013 37936 0 0
T4 349177 329242 0 0
T5 180178 86652 0 0
T6 301745 426589 0 0
T9 283840 138897 0 0
T17 267241 131469 0 0
T18 56101 20643 0 0
T19 193879 94973 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 445307016 139308202 0 0
DepthKnown_A 445307016 445199589 0 0
RvalidKnown_A 445307016 445199589 0 0
WreadyKnown_A 445307016 445199589 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 139308202 0 0
T1 36590 17252 0 0
T2 732 5 0 0
T3 273013 37936 0 0
T4 349177 148188 0 0
T5 180178 86652 0 0
T6 301745 426588 0 0
T9 283840 138897 0 0
T17 267241 131469 0 0
T18 56101 20643 0 0
T19 193879 94973 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 445307016 22533204 0 0
DepthKnown_A 445307016 445199589 0 0
RvalidKnown_A 445307016 445199589 0 0
WreadyKnown_A 445307016 445199589 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 22533204 0 0
T1 36590 6525 0 0
T2 732 0 0 0
T3 273013 7153 0 0
T4 349177 94024 0 0
T5 180178 32871 0 0
T6 301745 117064 0 0
T9 283840 34056 0 0
T17 267241 26332 0 0
T18 56101 4992 0 0
T19 193879 23103 0 0
T21 0 1151 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 445307016 33657178 0 0
DepthKnown_A 445307016 445199589 0 0
RvalidKnown_A 445307016 445199589 0 0
WreadyKnown_A 445307016 445199589 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 33657178 0 0
T1 36590 6525 0 0
T2 732 0 0 0
T3 273013 7153 0 0
T4 349177 422739 0 0
T5 180178 32871 0 0
T6 301745 117064 0 0
T9 283840 34056 0 0
T17 267241 26332 0 0
T18 56101 4992 0 0
T19 193879 23103 0 0
T21 0 5065 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 445307016 67604054 0 0
DepthKnown_A 445307016 445199589 0 0
RvalidKnown_A 445307016 445199589 0 0
WreadyKnown_A 445307016 445199589 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 67604054 0 0
T1 36590 10727 0 0
T2 732 5 0 0
T3 273013 30783 0 0
T4 349177 235206 0 0
T5 180178 53781 0 0
T6 301745 309525 0 0
T9 283840 104841 0 0
T17 267241 105137 0 0
T18 56101 15651 0 0
T19 193879 71870 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 445307016 105651024 0 0
DepthKnown_A 445307016 445199589 0 0
RvalidKnown_A 445307016 445199589 0 0
WreadyKnown_A 445307016 445199589 0 0
gen_passthru_fifo.paramCheckPass 660 660 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 105651024 0 0
T1 36590 10727 0 0
T2 732 5 0 0
T3 273013 30783 0 0
T4 349177 105914 0 0
T5 180178 53781 0 0
T6 301745 309524 0 0
T9 283840 104841 0 0
T17 267241 105137 0 0
T18 56101 15651 0 0
T19 193879 71870 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 445307016 445199589 0 0
T1 36590 36518 0 0
T2 732 673 0 0
T3 273013 272865 0 0
T4 349177 349110 0 0
T5 180178 180095 0 0
T6 301745 301730 0 0
T9 283840 283790 0 0
T17 267241 267161 0 0
T18 56101 56042 0 0
T19 193879 193814 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 660 660 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%