Unified Coverage Report :: Module :: prim_sha2_32

Module : prim_sha2_32

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.87	87.25	73.97			81.40

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_512	99.39	100.00	98.18			100.00

---

Module Instance : tb.dut.u_prim_sha2_512

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.39	100.00	98.18			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.47	98.60	96.71		90.00	96.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_multimode_logic.u_prim_sha2_multimode	95.07	98.13	96.42		90.00	95.74

Line Coverage for Module : prim_sha2_32

	Line No.	Total	Covered	Percent
TOTAL		102	89	87.25
CONT_ASSIGN	44	1	1	100.00
ALWAYS	65	89	76	85.39
ALWAYS	222	3	3	100.00
ALWAYS	227	3	3	100.00
ALWAYS	232	3	3	100.00
ALWAYS	237	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
74	2	2
75	1	1
77	1	1
78	1	1
79	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
91	1	1
93	1	1
94	1	1
96	1	1
97	1	1
98	1	1
99	1	1
			MISSING_ELSE
101	1	1
103	1	1
105	1	1
109	1	1
111	1	1
112	1	1
115	1	1
116	1	1
117	1	1
118	1	1
119	1	1
121	1	1
122	1	1
			MISSING_ELSE
124	1	1
126	1	1
127	1	1
128	1	1
130	1	1
131	1	1
133	0	1
135	0	1
136	0	1
137	0	1
138	0	1
139	0	1
			==> MISSING_ELSE
141	0	1
143	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
146	1	1
148	1	1
149	1	1
150	1	1
151	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
164	0	1
165	0	1
166	0	1
167	0	1
			==> MISSING_ELSE
169	1	1
170	0	1
			MISSING_ELSE
			MISSING_ELSE
175	1	1
176	1	1
177	1	1
178	1	1
180	1	1
184	2	2
185	2	2
186	1	1
189	2	2
190	2	2
191	1	1
222	2	2
223	1	1
227	2	2
228	1	1
232	2	2
233	1	1
237	2	2
238	1	1

---

Cond Coverage for Module : prim_sha2_32

	Total	Covered	Percent
Conditions	73	54	73.97
Logical	73	54	73.97
Non-Logical	0	0
Event	0	0

 LINE       44
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

 LINE       74
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (sha_en_i && fifo_rvalid_i)
             ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       78
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       79
 EXPRESSION (gen_multimode_logic.digest_mode_flag_q != SHA2_256)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       83
 EXPRESSION (fifo_st == FifoLoadFromFifo)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       98
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       109
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       121
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4

 LINE       124
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       133
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       138
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       141
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       149
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       149
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       149
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       151
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       151
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       151
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       160
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       162
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q))
             ------------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       162
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
                ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       162
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Not Covered
1	0	Not Covered

 LINE       166
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       169
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       175
 EXPRESSION (gen_multimode_logic.word_part_reset || hash_go || ((!sha_en_i)))
             -----------------1-----------------    ---2---    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T3,T4
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T3,T4

 LINE       189
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_sha2_32

	Line No.	Total	Covered	Percent
Branches		43	35	81.40
IF	74	2	2	100.00
IF	77	24	16	66.67
IF	175	3	3	100.00
IF	184	3	3	100.00
IF	189	3	3	100.00
IF	222	2	2	100.00
IF	227	2	2	100.00
IF	232	2	2	100.00
IF	237	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if (((!sha_en_i) || hash_go))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	77	if ((sha_en_i && fifo_rvalid_i))
-2-:	78	if ((gen_multimode_logic.word_part_count_q == 2'b0))
-3-:	79	if ((gen_multimode_logic.digest_mode_flag_q != SHA2_256))
-4-:	83	if ((fifo_st == FifoLoadFromFifo))
-5-:	98	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-6-:	101	if ((sha_ready == 1'b1))
-7-:	109	if ((gen_multimode_logic.word_part_count_q == 2'b1))
-8-:	121	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-9-:	124	if ((sha_ready == 1'b1))
-10-:	133	if ((gen_multimode_logic.word_part_count_q == 2'b10))
-11-:	138	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-12-:	141	if ((sha_ready == 1'b1))
-13-:	146	if (sha_en_i)
-14-:	149	if (((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-15-:	151	if (((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-16-:	157	if ((sha_ready == 1'b1))
-17-:	160	if ((gen_multimode_logic.word_part_count_q == 2'b1))
-18-:	162	if (((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-19-:	166	if ((sha_ready == 1'b1))
-20-:	169	if ((gen_multimode_logic.word_part_count_q == 2'b10))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	Status	Tests
1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	1	0	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	1	0	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
1	0	-	-	-	-	0	-	-	1	1	-	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	-	0	-	-	1	0	-	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	-	0	-	-	1	-	1	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	-	0	-	-	1	-	0	-	-	-	-	-	-	-	-	Not Covered
1	0	-	-	-	-	0	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
0	-	-	-	-	-	-	-	-	-	-	-	1	0	1	1	-	-	-	-	Covered	T1,T3,T4
0	-	-	-	-	-	-	-	-	-	-	-	1	0	1	0	-	-	-	-	Covered	T1,T3,T4
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	1	-	-	-	Covered	T1,T3,T4
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	1	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	0	-	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	1	Not Covered
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	0	Covered	T1,T3,T4
0	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	175	if (((gen_multimode_logic.word_part_reset || hash_go) || (!sha_en_i)))
-2-:	177	if (gen_multimode_logic.word_part_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	184	if (hash_go)
-2-:	185	if (hash_done_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	189	if (((!sha_en_i) || hash_go))
-2-:	190	if (hash_process_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	222	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	227	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	232	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	237	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_sha2_512

	Line No.	Total	Covered	Percent
TOTAL		89	89	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	65	76	76	100.00
ALWAYS	222	3	3	100.00
ALWAYS	227	3	3	100.00
ALWAYS	232	3	3	100.00
ALWAYS	237	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
74	2	2
75	1	1
77	1	1
78	1	1
79	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
91	1	1
93	1	1
94	1	1
96	1	1
97	1	1
98	1	1
99	1	1
			MISSING_ELSE
101	1	1
103	1	1
105	1	1
109	1	1
111	1	1
112	1	1
115	1	1
116	1	1
117	1	1
118	1	1
119	1	1
121	1	1
122	1	1
			MISSING_ELSE
124	1	1
126	1	1
127	1	1
128	1	1
130	1	1
131	1	1
133		excluded
			Exclude Annotation: VC_COV_UNR
135		excluded
			Exclude Annotation: VC_COV_UNR
136		excluded
			Exclude Annotation: VC_COV_UNR
137		excluded
			Exclude Annotation: VC_COV_UNR
138		excluded
			Exclude Annotation: VC_COV_UNR
139		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
141		excluded
			Exclude Annotation: VC_COV_UNR
143		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
			==> MISSING_ELSE
146	1	1
148	1	1
149	1	1
150	1	1
151	1	1
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
164		excluded
			Exclude Annotation: VC_COV_UNR
165		excluded
			Exclude Annotation: VC_COV_UNR
166		excluded
			Exclude Annotation: VC_COV_UNR
167		excluded
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE
169	1	1
170		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
			MISSING_ELSE
175	1	1
176	1	1
177	1	1
178	1	1
180	1	1
184	2	2
185	2	2
186	1	1
189	2	2
190	2	2
191	1	1
222	2	2
223	1	1
227	2	2
228	1	1
232	2	2
233	1	1
237	2	2
238	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_sha2_512

	Total	Covered	Percent
Conditions	55	54	98.18
Logical	55	54	98.18
Non-Logical	0	0
Event	0	0

 LINE       44
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

 LINE       74
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (sha_en_i && fifo_rvalid_i)
             ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       78
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       79
 EXPRESSION (gen_multimode_logic.digest_mode_flag_q != SHA2_256)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       83
 EXPRESSION (fifo_st == FifoLoadFromFifo)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       98
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       109
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T3,T4

 LINE       121
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T4

 LINE       124
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T4

 LINE       133
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       138
 EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
             -------1------    -----------------2----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		VC_COV_UNR
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

 LINE       141
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       149
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       149
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b0)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       149
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       151
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q))
             -----------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       151
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
                -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       151
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       160
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b1)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       162
 EXPRESSION ((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q))
             ------------------------1-----------------------    ---------------------------2--------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       162
 SUB-EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
                ------------------------1-----------------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T3,T4
1	Excluded		VC_COV_UNR

 LINE       162
 SUB-EXPRESSION (hash_process_i || gen_multimode_logic.process_flag_q)
                 -------1------    -----------------2----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T3,T4
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR

 LINE       166
 EXPRESSION (sha_ready == 1'b1)
            ---------1---------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Excluded		VC_COV_UNR

 LINE       169
 EXPRESSION (gen_multimode_logic.word_part_count_q == 2'b10)
            ------------------------1-----------------------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T3,T4
1	Excluded		VC_COV_UNR

 LINE       175
 EXPRESSION (gen_multimode_logic.word_part_reset || hash_go || ((!sha_en_i)))
             -----------------1-----------------    ---2---    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T3,T4
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T3,T4
1	0	0	Covered	T1,T3,T4

 LINE       189
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_prim_sha2_512

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
IF	74	2	2	100.00
IF	77	16	16	100.00
IF	175	3	3	100.00
IF	184	3	3	100.00
IF	189	3	3	100.00
IF	222	2	2	100.00
IF	227	2	2	100.00
IF	232	2	2	100.00
IF	237	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_32.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	if (((!sha_en_i) || hash_go))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	77	if ((sha_en_i && fifo_rvalid_i))
-2-:	78	if ((gen_multimode_logic.word_part_count_q == 2'b0))
-3-:	79	if ((gen_multimode_logic.digest_mode_flag_q != SHA2_256))
-4-:	83	if ((fifo_st == FifoLoadFromFifo))
-5-:	98	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-6-:	101	if ((sha_ready == 1'b1))
-7-:	109	if ((gen_multimode_logic.word_part_count_q == 2'b1))
-8-:	121	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-9-:	124	if ((sha_ready == 1'b1))
-10-:	133	if ((gen_multimode_logic.word_part_count_q == 2'b10))
-11-:	138	if ((hash_process_i || gen_multimode_logic.process_flag_q))
-12-:	141	if ((sha_ready == 1'b1))
-13-:	146	if (sha_en_i)
-14-:	149	if (((gen_multimode_logic.word_part_count_q == 2'b0) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-15-:	151	if (((gen_multimode_logic.word_part_count_q == 2'b1) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-16-:	157	if ((sha_ready == 1'b1))
-17-:	160	if ((gen_multimode_logic.word_part_count_q == 2'b1))
-18-:	162	if (((gen_multimode_logic.word_part_count_q == 2'b10) && (hash_process_i || gen_multimode_logic.process_flag_q)))
-19-:	166	if ((sha_ready == 1'b1))
-20-:	169	if ((gen_multimode_logic.word_part_count_q == 2'b10))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	Status	Tests	Exclude Annotation
1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	1	0	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	1	0	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
1	0	-	-	-	-	1	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
1	0	-	-	-	-	0	-	-	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
1	0	-	-	-	-	0	-	-	1	0	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
1	0	-	-	-	-	0	-	-	1	-	1	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
1	0	-	-	-	-	0	-	-	1	-	0	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
1	0	-	-	-	-	0	-	-	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
0	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
0	-	-	-	-	-	-	-	-	-	-	-	1	0	1	1	-	-	-	-	Covered	T1,T3,T4
0	-	-	-	-	-	-	-	-	-	-	-	1	0	1	0	-	-	-	-	Covered	T1,T3,T4
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	1	-	-	-	Covered	T1,T3,T4
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	1	-	Excluded		VC_COV_UNR
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	1	0	-	Excluded		VC_COV_UNR
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	1	Excluded		VC_COV_UNR
0	-	-	-	-	-	-	-	-	-	-	-	1	0	0	-	0	0	-	0	Covered	T1,T3,T4
0	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	175	if (((gen_multimode_logic.word_part_reset || hash_go) || (!sha_en_i)))
-2-:	177	if (gen_multimode_logic.word_part_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	184	if (hash_go)
-2-:	185	if (hash_done_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	189	if (((!sha_en_i) || hash_go))
-2-:	190	if (hash_process_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	222	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	227	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	232	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	237	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3