Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44567726

1

T1

9

T2

1284

T3

1

full_word

39795197

1

T1

9

T2

1184

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	84362543	1			T1	18		T2	2468		T3	2
auto[TlIntgErrCmd]	140	1			T72	11		T73	8		T74	6
auto[TlIntgErrData]	131	1			T72	10		T73	8		T74	3
auto[TlIntgErrBoth]	109	1			T72	9		T73	4		T74	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39570317

1

T1

1

T2

1386

T3

1

auto[1]

44792606

1

T1

17

T2

1082

T3

1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20444380	1			T2	811		T7	43422		T4	4634
auto[TlIntgErrNone]	partial	auto[1]	24123005	1			T1	9		T2	473		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	19125774	1			T1	1		T2	575		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	20669384	1			T1	8		T2	609		T7	37560
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T72	3		T73	2		T74	2
auto[TlIntgErrCmd]	partial	auto[1]	77	1			T72	6		T73	5		T74	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T74	1		T124	1		T126	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T72	2		T73	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T72	5		T73	5		T74	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T72	5		T73	3		T123	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T124	1		T126	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T129	1		T126	1		T130	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T72	4		T73	1		T123	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T72	4		T73	2		T74	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T72	1		T73	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T131	1		T127	1		T124	2