Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	498635813	1691629	0	0
intr_enable_rd_A	498635813	4368	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498635813	1691629	0	0
T9	740508	180908	0	0
T10	0	71868	0	0
T11	0	142692	0	0
T12	91075	0	0	0
T15	0	127480	0	0
T16	0	26958	0	0
T24	0	216131	0	0
T25	0	118665	0	0
T26	0	80030	0	0
T29	0	113241	0	0
T35	313415	0	0	0
T36	979084	0	0	0
T37	692272	0	0	0
T38	329736	0	0	0
T39	305631	0	0	0
T40	216563	0	0	0
T41	268809	0	0	0
T75	0	105547	0	0
T76	65369	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498635813	4368	0	0
T5	897495	57	0	0
T6	758676	0	0	0
T8	33848	0	0	0
T10	0	19	0	0
T15	0	94	0	0
T16	0	57	0	0
T17	63943	0	0	0
T18	494903	0	0	0
T22	548880	0	0	0
T23	676184	0	0	0
T27	836902	0	0	0
T28	40677	0	0	0
T56	1115	0	0	0
T69	0	35	0	0
T77	0	128	0	0
T78	0	1	0	0
T79	0	22	0	0
T80	0	28	0	0
T81	0	24	0	0