Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44010939

1

T1

47759

T2

73267

T3

90066

full_word

38960660

1

T1

37622

T2

62871

T3

70244

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	82971179	1			T1	85381		T2	136138		T3	160310
auto[TlIntgErrCmd]	123	1			T62	5		T63	5		T64	12
auto[TlIntgErrData]	169	1			T62	3		T63	14		T64	11
auto[TlIntgErrBoth]	128	1			T62	2		T63	11		T64	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39139035

1

T1

42916

T2

66725

T3

80330

auto[1]

43832564

1

T1

42465

T2

69413

T3

79980

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20159112	1			T1	21566		T2	33285		T3	40372
auto[TlIntgErrNone]	partial	auto[1]	23851443	1			T1	26193		T2	39982		T3	49694
auto[TlIntgErrNone]	full_word	auto[0]	18979734	1			T1	21350		T2	33440		T3	39958
auto[TlIntgErrNone]	full_word	auto[1]	19980890	1			T1	16272		T2	29431		T3	30286
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T62	3		T63	2		T64	5
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T62	2		T63	3		T64	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T64	1		T115	1		T116	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1			T64	1		T113	1		T65	2
auto[TlIntgErrData]	partial	auto[0]	76	1			T62	1		T63	9		T64	4
auto[TlIntgErrData]	partial	auto[1]	84	1			T62	2		T63	3		T64	7
auto[TlIntgErrData]	full_word	auto[0]	6	1			T63	2		T113	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T117	1		T118	1		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T62	1		T63	3		T64	4
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T63	8		T64	3		T117	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T113	1		T119	1		T120	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T62	1		T117	1		T121	1