Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	434695807	1549173	0	0
intr_enable_rd_A	434695807	3456	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434695807	1549173	0	0
T6	139872	273173	0	0
T7	0	41081	0	0
T8	0	56221	0	0
T12	0	88385	0	0
T13	0	28332	0	0
T14	0	154518	0	0
T19	141632	0	0	0
T20	35796	0	0	0
T21	0	47170	0	0
T22	0	74085	0	0
T36	0	105239	0	0
T56	245052	0	0	0
T57	970385	0	0	0
T58	471146	0	0	0
T59	40532	0	0	0
T60	534213	0	0	0
T61	204712	0	0	0
T66	0	52049	0	0
T67	9670	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434695807	3456	0	0
T12	0	167	0	0
T13	0	35	0	0
T14	0	68	0	0
T19	141632	0	0	0
T20	35796	0	0	0
T56	245052	8	0	0
T57	970385	0	0	0
T58	471146	0	0	0
T59	40532	0	0	0
T60	534213	0	0	0
T61	204712	0	0	0
T67	9670	0	0	0
T68	0	29	0	0
T69	0	8	0	0
T70	0	16	0	0
T71	0	36	0	0
T72	0	76	0	0
T73	0	39	0	0
T74	467434	0	0	0