Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

44448975

1

T1

6965

T2

75606

T3

234908

full_word

39504934

1

T1

11162

T2

58872

T3

237067

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	83953489	1			T1	18127		T2	134478		T3	471975
auto[TlIntgErrCmd]	120	1			T60	10		T61	7		T62	4
auto[TlIntgErrData]	140	1			T60	8		T61	6		T62	4
auto[TlIntgErrBoth]	160	1			T60	12		T61	7		T62	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39603416

1

T1

8088

T2

67389

T3

222711

auto[1]

44350493

1

T1

10039

T2

67089

T3

249264

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20376895	1			T1	5751		T2	33889		T3	113067
auto[TlIntgErrNone]	partial	auto[1]	24071689	1			T1	1214		T2	41717		T3	121841
auto[TlIntgErrNone]	full_word	auto[0]	19226337	1			T1	2337		T2	33500		T3	109644
auto[TlIntgErrNone]	full_word	auto[1]	20278568	1			T1	8825		T2	25372		T3	127423
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T60	5		T61	3		T62	1
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T60	5		T61	2		T62	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T61	1		T62	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T61	1		T114	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T60	4		T61	3		T62	2
auto[TlIntgErrData]	partial	auto[1]	77	1			T60	2		T61	3		T62	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T60	2		T62	1		T112	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T112	1		T116	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	68	1			T60	6		T61	4		T62	1
auto[TlIntgErrBoth]	partial	auto[1]	80	1			T60	6		T61	2		T112	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T61	1		T112	2		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T62	1		T118	1		T119	1