Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	485671851	1502792	0	0
intr_enable_rd_A	485671851	4717	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485671851	1502792	0	0
T7	117344	16133	0	0
T8	0	236896	0	0
T9	0	133648	0	0
T13	0	97647	0	0
T14	0	86167	0	0
T19	85357	0	0	0
T22	0	63054	0	0
T56	807	0	0	0
T63	0	49712	0	0
T64	0	53444	0	0
T65	0	229475	0	0
T66	0	70804	0	0
T67	31206	0	0	0
T68	62648	0	0	0
T69	217242	0	0	0
T70	260031	0	0	0
T71	145078	0	0	0
T72	153733	0	0	0
T73	122416	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485671851	4717	0	0
T3	432001	42	0	0
T4	52852	0	0	0
T5	326528	0	0	0
T6	387841	0	0	0
T7	0	53	0	0
T13	0	128	0	0
T15	7349	0	0	0
T16	1034	0	0	0
T17	343714	0	0	0
T18	553314	0	0	0
T21	139987	0	0	0
T27	873980	0	0	0
T71	0	12	0	0
T74	0	26	0	0
T75	0	45	0	0
T76	0	23	0	0
T77	0	33	0	0
T78	0	1	0	0
T79	0	80	0	0