Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42498073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40166110

1

T1

17686

T2

3

T4

1571

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39375061	1			T1	20267		T2	1		T3	1
values[0x0]	20275285	1			T1	9235		T2	8		T3	2
values[0x1]	23013837	1			T1	11021		T2	6		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32677266	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

49986917

1

T1

22864

T2

3

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	266835	1			T1	150		T2	2		T5	81
valid_sources[0x01]	261801	1			T1	152		T5	79		T10	7100
valid_sources[0x02]	276794	1			T1	153		T5	71		T10	7128
valid_sources[0x03]	267748	1			T1	154		T5	73		T10	7308
valid_sources[0x04]	262591	1			T1	157		T5	90		T10	7174
valid_sources[0x05]	257218	1			T1	186		T5	67		T10	7154
valid_sources[0x06]	263307	1			T1	129		T5	52		T10	7126
valid_sources[0x07]	281978	1			T1	174		T5	74		T10	7165
valid_sources[0x08]	260141	1			T1	153		T5	95		T10	7222
valid_sources[0x09]	685803	1			T1	153		T5	76		T10	7083
valid_sources[0x0a]	320992	1			T1	180		T5	66		T10	7089
valid_sources[0x0b]	277978	1			T1	153		T5	84		T10	7266
valid_sources[0x0c]	268935	1			T1	163		T5	93		T10	7289
valid_sources[0x0d]	267866	1			T1	143		T5	75		T10	7369
valid_sources[0x0e]	264115	1			T1	154		T5	96		T10	7205
valid_sources[0x0f]	268726	1			T1	169		T5	71		T10	6890
valid_sources[0x10]	727631	1			T1	155		T5	77		T10	7390
valid_sources[0x11]	357156	1			T1	128		T5	84		T10	7203
valid_sources[0x12]	257866	1			T1	153		T5	97		T10	7296
valid_sources[0x13]	270222	1			T1	156		T5	74		T10	7095
valid_sources[0x14]	266378	1			T1	179		T5	91		T10	7200
valid_sources[0x15]	261203	1			T1	128		T5	72		T10	7247
valid_sources[0x16]	269057	1			T1	169		T5	70		T10	7160
valid_sources[0x17]	268596	1			T1	166		T5	70		T10	7090
valid_sources[0x18]	256893	1			T1	152		T5	69		T10	7199
valid_sources[0x19]	300261	1			T1	147		T5	65		T10	7249
valid_sources[0x1a]	278884	1			T1	149		T5	96		T10	7251
valid_sources[0x1b]	275153	1			T1	167		T5	78		T10	7145
valid_sources[0x1c]	480851	1			T1	167		T5	72		T10	7211
valid_sources[0x1d]	262594	1			T1	148		T5	80		T10	7202
valid_sources[0x1e]	269666	1			T1	158		T5	92		T10	7211
valid_sources[0x1f]	264772	1			T1	163		T5	72		T10	7135
valid_sources[0x20]	348103	1			T1	161		T5	78		T10	7148
valid_sources[0x21]	264508	1			T1	185		T5	80		T10	6941
valid_sources[0x22]	262737	1			T1	156		T5	71		T10	7286
valid_sources[0x23]	275628	1			T1	185		T5	80		T10	7095
valid_sources[0x24]	344617	1			T1	154		T5	90		T10	7304
valid_sources[0x25]	270772	1			T1	154		T5	97		T10	7285
valid_sources[0x26]	273640	1			T1	167		T5	73		T10	7213
valid_sources[0x27]	258501	1			T1	140		T5	88		T10	7026
valid_sources[0x28]	266829	1			T1	146		T5	79		T10	7116
valid_sources[0x29]	270132	1			T1	170		T5	81		T10	7146
valid_sources[0x2a]	372837	1			T1	155		T5	81		T10	7198
valid_sources[0x2b]	285045	1			T1	161		T5	93		T10	7213
valid_sources[0x2c]	262147	1			T1	152		T5	89		T10	7145
valid_sources[0x2d]	418466	1			T1	157		T5	62		T10	7252
valid_sources[0x2e]	270983	1			T1	153		T5	85		T10	7178
valid_sources[0x2f]	270919	1			T1	138		T16	2		T5	96
valid_sources[0x30]	401543	1			T1	124		T5	81		T10	7142
valid_sources[0x31]	257542	1			T1	138		T5	85		T10	7242
valid_sources[0x32]	265366	1			T1	154		T5	75		T10	7185
valid_sources[0x33]	273150	1			T1	151		T5	84		T10	7263
valid_sources[0x34]	269057	1			T1	158		T5	90		T10	7223
valid_sources[0x35]	265454	1			T1	146		T5	69		T10	7244
valid_sources[0x36]	272452	1			T1	171		T5	99		T10	7128
valid_sources[0x37]	274731	1			T1	143		T5	89		T10	7072
valid_sources[0x38]	367890	1			T1	133		T5	68		T10	7271
valid_sources[0x39]	264659	1			T1	154		T2	1		T16	1
valid_sources[0x3a]	272312	1			T1	149		T5	79		T10	7306
valid_sources[0x3b]	450571	1			T1	167		T5	84		T10	7308
valid_sources[0x3c]	258607	1			T1	149		T5	70		T10	7088
valid_sources[0x3d]	267152	1			T1	156		T5	78		T10	7289
valid_sources[0x3e]	257571	1			T1	189		T5	102		T10	7073
valid_sources[0x3f]	492941	1			T1	143		T5	93		T10	6960
valid_sources[0x40]	264916	1			T1	126		T5	94		T10	7301
valid_sources[0x41]	273836	1			T1	144		T5	80		T10	7199
valid_sources[0x42]	330627	1			T1	165		T5	83		T10	7177
valid_sources[0x43]	307893	1			T1	151		T5	80		T10	7253
valid_sources[0x44]	484638	1			T1	169		T5	73		T10	7307
valid_sources[0x45]	275170	1			T1	164		T5	77		T10	7206
valid_sources[0x46]	304982	1			T1	171		T5	74		T10	7000
valid_sources[0x47]	268538	1			T1	141		T5	84		T10	7139
valid_sources[0x48]	1258823	1			T1	138		T2	1		T5	82
valid_sources[0x49]	273178	1			T1	141		T5	72		T10	7258
valid_sources[0x4a]	868615	1			T1	150		T5	89		T10	7257
valid_sources[0x4b]	466401	1			T1	153		T5	70		T10	7228
valid_sources[0x4c]	428529	1			T1	161		T5	66		T10	7066
valid_sources[0x4d]	265440	1			T1	153		T5	80		T10	7233
valid_sources[0x4e]	270561	1			T1	155		T5	103		T10	7307
valid_sources[0x4f]	260550	1			T1	156		T5	96		T10	7252
valid_sources[0x50]	267235	1			T1	150		T5	64		T10	7325
valid_sources[0x51]	263847	1			T1	162		T5	85		T10	7225
valid_sources[0x52]	306653	1			T1	148		T5	89		T10	7062
valid_sources[0x53]	1409862	1			T1	149		T2	1		T5	97
valid_sources[0x54]	361767	1			T1	143		T5	87		T10	7266
valid_sources[0x55]	338802	1			T1	148		T5	74		T10	7383
valid_sources[0x56]	264775	1			T1	157		T5	76		T10	7190
valid_sources[0x57]	267502	1			T1	175		T5	80		T10	7152
valid_sources[0x58]	310693	1			T1	156		T2	1		T5	89
valid_sources[0x59]	264574	1			T1	161		T5	93		T10	7100
valid_sources[0x5a]	257159	1			T1	156		T5	65		T10	7172
valid_sources[0x5b]	272470	1			T1	162		T5	82		T10	7240
valid_sources[0x5c]	300617	1			T1	154		T5	78		T10	7416
valid_sources[0x5d]	344326	1			T1	148		T5	92		T10	7265
valid_sources[0x5e]	277645	1			T1	162		T5	74		T10	7331
valid_sources[0x5f]	266172	1			T1	160		T5	87		T10	7342
valid_sources[0x60]	267929	1			T1	184		T5	83		T10	7201
valid_sources[0x61]	265978	1			T1	200		T5	93		T10	7321
valid_sources[0x62]	316319	1			T1	177		T5	85		T10	7335
valid_sources[0x63]	276773	1			T1	160		T5	73		T10	7374
valid_sources[0x64]	271543	1			T1	180		T4	2695		T5	80
valid_sources[0x65]	335247	1			T1	151		T5	72		T10	7254
valid_sources[0x66]	263429	1			T1	179		T5	85		T10	7329
valid_sources[0x67]	274058	1			T1	176		T5	84		T10	7193
valid_sources[0x68]	265763	1			T1	170		T5	68		T10	7159
valid_sources[0x69]	266265	1			T1	157		T5	96		T10	7278
valid_sources[0x6a]	271179	1			T1	169		T3	11		T5	108
valid_sources[0x6b]	281564	1			T1	183		T5	100		T10	7396
valid_sources[0x6c]	460926	1			T1	154		T5	59		T10	7265
valid_sources[0x6d]	255938	1			T1	165		T5	77		T10	7136
valid_sources[0x6e]	313775	1			T1	184		T5	62		T10	7205
valid_sources[0x6f]	272941	1			T1	144		T5	61		T10	7238
valid_sources[0x70]	267672	1			T1	151		T5	65		T10	7233
valid_sources[0x71]	266530	1			T1	151		T5	92		T10	7245
valid_sources[0x72]	272202	1			T1	182		T2	1		T5	90
valid_sources[0x73]	277348	1			T1	180		T5	89		T10	7146
valid_sources[0x74]	262234	1			T1	144		T5	81		T10	7185
valid_sources[0x75]	398679	1			T1	156		T5	76		T10	7304
valid_sources[0x76]	323718	1			T1	152		T5	70		T10	7151
valid_sources[0x77]	267678	1			T1	174		T2	1		T5	69
valid_sources[0x78]	275738	1			T1	177		T5	79		T10	7053
valid_sources[0x79]	310436	1			T1	171		T5	79		T10	7133
valid_sources[0x7a]	270610	1			T1	185		T5	89		T10	7281
valid_sources[0x7b]	268061	1			T1	146		T5	89		T10	7193
valid_sources[0x7c]	308230	1			T1	154		T5	86		T10	7100
valid_sources[0x7d]	284793	1			T1	150		T5	101		T10	7059
valid_sources[0x7e]	266172	1			T1	156		T5	89		T10	7196
valid_sources[0x7f]	261547	1			T1	142		T5	70		T10	7196
valid_sources[0x80]	271263	1			T1	163		T5	83		T10	7187

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19438669

1

T1

10026

T2

1

T4

513

values[0x0]

all_enables

biggest_size

11165713

1

T1

4209

T2

2

T4

544

values[0x1]

all_enables

biggest_size

9561728

1

T1

3451

T4

514

T5

6971