Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

45772119

1

T1

22837

T2

12

T3

11

full_word

40378419

1

T1

17686

T2

3

T4

1571

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	86150158	1			T1	40523		T2	15		T3	11
auto[TlIntgErrCmd]	128	1			T62	9		T63	6		T64	5
auto[TlIntgErrData]	126	1			T62	6		T64	6		T112	1
auto[TlIntgErrBoth]	126	1			T62	5		T63	4		T64	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

40475064

1

T1

20267

T2

1

T3

1

auto[1]

45675474

1

T1

20256

T2

14

T3

10

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20952472	1			T1	10241		T3	1		T4	628
auto[TlIntgErrNone]	partial	auto[1]	24819300	1			T1	12596		T2	12		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	19522420	1			T1	10026		T2	1		T4	513
auto[TlIntgErrNone]	full_word	auto[1]	20855966	1			T1	7660		T2	2		T4	1058
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T62	3		T63	1		T64	3
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T62	5		T63	4		T64	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T62	1		T113	1		T114	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T63	1		T112	2		T115	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T62	3		T64	2		T113	8
auto[TlIntgErrData]	partial	auto[1]	51	1			T62	3		T64	3		T112	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T64	1		T116	1		T117	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T114	1		T116	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T62	3		T64	1		T112	2
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T62	2		T63	4		T64	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T64	1		T113	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T64	1		T112	1		T113	1