Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : hmac_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.hmac_csr_assert 100.00 100.00



Module Instance : tb.dut.hmac_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.71 100.00 93.33 100.00 100.00 98.90 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : hmac_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 423636221 1873418 0 0
intr_enable_rd_A 423636221 2772 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 423636221 1873418 0 0
T6 626631 233627 0 0
T7 892487 0 0 0
T8 505038 0 0 0
T9 845998 0 0 0
T11 0 50189 0 0
T12 0 147314 0 0
T15 0 34553 0 0
T17 122357 0 0 0
T19 0 117222 0 0
T20 0 140993 0 0
T21 0 226871 0 0
T22 744470 0 0 0
T24 9590 0 0 0
T28 0 200610 0 0
T31 231907 0 0 0
T32 254485 0 0 0
T33 123341 0 0 0
T65 0 19195 0 0
T66 0 366 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 423636221 2772 0 0
T11 0 143 0 0
T15 0 32 0 0
T45 159917 19 0 0
T48 5126 0 0 0
T67 0 18 0 0
T68 0 17 0 0
T69 0 25 0 0
T70 0 13 0 0
T71 0 13 0 0
T72 0 57 0 0
T73 0 58 0 0
T74 38397 0 0 0
T75 1083 0 0 0
T76 37958 0 0 0
T77 15073 0 0 0
T78 839543 0 0 0
T79 26747 0 0 0
T80 817 0 0 0
T81 240711 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%