Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.10	100.00	93.75			86.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_packer	97.51	100.00	93.75			96.30	100.00

---

Module Instance : tb.dut.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.51	100.00	93.75			96.30	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.51	100.00	93.75			96.30	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.71	100.00	93.33	100.00	100.00	98.90	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		66	66	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	78	6	6	100.00
ALWAYS	90	5	5	100.00
ALWAYS	157	4	4	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	185	9	9	100.00
ALWAYS	214	8	8	100.00
ALWAYS	235	3	3	100.00
ALWAYS	243	14	14	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	291	0	0
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
78	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
90	1	1
91	1	1
92	1	1
93	1	1
95	1	1
157	1	1
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	1	1
166	1	1
170	1	1
171	1	1
174	1	1
175	1	1
178	1	1
180	1	1
185	1	1
187	1	1
188	1	1
192	1	1
193	1	1
197	1	1
198	1	1
202	1	1
203	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
235	1	1
236	1	1
238	1	1
243	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
253	1	1
258	1	1
259	1	1
261	1	1
262	1	1
264	1	1
266	1	1
267	1	1
279	1	1
283	1	1
291		unreachable
294	1	1
295	1	1
296	1	1
299		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 7'(OutW))))
             ----------1----------

-1-	Status	Tests
0	Unreachable	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 7'(OutW))))
             ---------------1--------------

-1-	Status	Tests
0	Unreachable	T13,T26,T27
1	Not Covered

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T9,T13,T14
1	1	Covered	T1,T4,T5

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T13,T23
1	1	Covered	T1,T4,T5

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T4,T5

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		30	26	86.67
TERNARY	170	2	2	100.00
TERNARY	171	2	2	100.00
TERNARY	283	1	1	100.00
IF	159	2	2	100.00
CASE	185	5	4	80.00
IF	214	3	3	100.00
IF	235	2	2	100.00
CASE	248	5	4	80.00
CASE	80	5	3	60.00
IF	90	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Covered	T1,T2,T3
2'b01	Covered	T1,T4,T5
2'b10	Covered	T1,T4,T5
2'b11	Covered	T13,T26,T27
default	Not Covered

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	217	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	case (flush_st)
-2-:	250	if (flush_i)
-3-:	258	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T1,T4,T5
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T1,T4,T5
FlushSend	-	0	Covered	T1,T4,T5
default	-	-	Not Covered

	LineNo.	Expression
-1-:	80	case ({ack_in, ack_out})
-2-:	82	((int'(pos_q) <= OutW)) ? 
-3-:	84	((int'(pos_with_input) <= OutW)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
2'b00	-	-	Covered	T1,T2,T3
2'b01	1	-	Covered	T1,T4,T5
2'b01	0	-	Unreachable	T1,T4,T5
2'b10	-	-	Covered	T1,T4,T5
2'b11	-	1	Not Covered
2'b11	-	0	Unreachable	T13,T26,T27
default	-	-	Not Covered

	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	397277403	139	0	492
DataOStableWhenPending_A	397277403	261	0	492
ExFlushValid_M	397277403	17767	0	0
ExcessiveDataStored_A	397277403	3	0	0
ExcessiveMaskStored_A	397277403	3	0	0
FlushFollowedByDone_A	397277403	17767	0	492
ValidIDeassertedOnFlush_M	397277403	28610	0	0
ValidOAssertedForStoredDataGTEOutW_A	397277403	7495919	0	0
ValidOPairedWidthReadyI_A	397277403	261	0	0
gen_mask_assert.ContiguousOnesMask_M	397277403	9785373	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	139	0	492
T9	845998	2	0	1
T13	0	7	0	0
T14	0	2	0	0
T20	0	24	0	0
T22	744470	0	0	1
T24	9590	0	0	1
T26	0	25	0	0
T27	0	10	0	0
T28	0	9	0	0
T29	0	41	0	0
T30	0	19	0	0
T31	231907	0	0	1
T32	254485	0	0	1
T33	123341	0	0	1
T34	817	0	0	1
T35	156525	0	0	1
T36	1232	0	0	1
T37	1221	0	0	1

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	261	0	492
T9	845998	8	0	1
T13	0	52	0	0
T14	0	8	0	0
T20	0	31	0	0
T22	744470	0	0	1
T23	0	2	0	0
T24	9590	0	0	1
T26	0	36	0	0
T27	0	12	0	0
T28	0	21	0	0
T29	0	57	0	0
T30	0	34	0	0
T31	231907	0	0	1
T32	254485	0	0	1
T33	123341	0	0	1
T34	817	0	0	1
T35	156525	0	0	1
T36	1232	0	0	1
T37	1221	0	0	1

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	17767	0	0
T1	83190	2	0	0
T2	743	0	0	0
T3	1242	0	0	0
T4	6847	2	0	0
T5	221190	11	0	0
T6	626631	180	0	0
T7	892487	20	0	0
T8	0	15	0	0
T9	0	116	0	0
T10	373060	386	0	0
T16	1183	0	0	0
T17	122357	3	0	0
T24	0	3	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	3	0	0
T13	159601	1	0	0
T25	168238	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T38	734744	0	0	0
T39	1214	0	0	0
T40	599271	0	0	0
T41	260349	0	0	0
T42	324317	0	0	0
T43	15208	0	0	0
T44	41861	0	0	0
T45	159917	0	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	3	0	0
T13	159601	1	0	0
T25	168238	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T38	734744	0	0	0
T39	1214	0	0	0
T40	599271	0	0	0
T41	260349	0	0	0
T42	324317	0	0	0
T43	15208	0	0	0
T44	41861	0	0	0
T45	159917	0	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	17767	0	492
T1	83190	2	0	1
T2	743	0	0	1
T3	1242	0	0	1
T4	6847	2	0	1
T5	221190	11	0	1
T6	626631	180	0	1
T7	892487	20	0	1
T8	0	15	0	0
T9	0	116	0	0
T10	373060	386	0	1
T16	1183	0	0	1
T17	122357	3	0	1
T24	0	3	0	0

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	28610	0	0
T1	83190	4	0	0
T2	743	0	0	0
T3	1242	0	0	0
T4	6847	4	0	0
T5	221190	20	0	0
T6	626631	310	0	0
T7	892487	33	0	0
T8	0	23	0	0
T9	0	209	0	0
T10	373060	674	0	0
T16	1183	0	0	0
T17	122357	6	0	0
T24	0	5	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	7495919	0	0
T1	83190	1984	0	0
T2	743	0	0	0
T3	1242	0	0	0
T4	6847	891	0	0
T5	221190	6755	0	0
T6	626631	106579	0	0
T7	892487	8471	0	0
T8	0	5506	0	0
T9	0	55680	0	0
T10	373060	212416	0	0
T16	1183	0	0	0
T17	122357	4544	0	0
T24	0	112	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	261	0	0
T9	845998	8	0	0
T13	0	52	0	0
T14	0	8	0	0
T20	0	31	0	0
T22	744470	0	0	0
T23	0	2	0	0
T24	9590	0	0	0
T26	0	36	0	0
T27	0	12	0	0
T28	0	21	0	0
T29	0	57	0	0
T30	0	34	0	0
T31	231907	0	0	0
T32	254485	0	0	0
T33	123341	0	0	0
T34	817	0	0	0
T35	156525	0	0	0
T36	1232	0	0	0
T37	1221	0	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	9785373	0	0
T1	83190	2760	0	0
T2	743	0	0	0
T3	1242	0	0	0
T4	6847	954	0	0
T5	221190	6786	0	0
T6	626631	134822	0	0
T7	892487	11811	0	0
T8	0	7648	0	0
T9	0	59338	0	0
T10	373060	294667	0	0
T16	1183	0	0	0
T17	122357	6371	0	0
T24	0	165	0	0

Line Coverage for Instance : tb.dut.u_packer

	Line No.	Total	Covered	Percent
TOTAL		66	66	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	78	6	6	100.00
ALWAYS	90	5	5	100.00
ALWAYS	157	4	4	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	185	9	9	100.00
ALWAYS	214	8	8	100.00
ALWAYS	235	3	3	100.00
ALWAYS	243	14	14	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	283	1	1	100.00
CONT_ASSIGN	291	0	0
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
78	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
			Exclude Annotation: VC_COV_UNR
90	1	1
91	1	1
92	1	1
93	1	1
95	1	1
157	1	1
158	1	1
159	1	1
160	1	1
			MISSING_ELSE
165	1	1
166	1	1
170	1	1
171	1	1
174	1	1
175	1	1
178	1	1
180	1	1
185	1	1
187	1	1
188	1	1
192	1	1
193	1	1
197	1	1
198	1	1
202	1	1
203	1	1
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
221	1	1
222	1	1
235	1	1
236	1	1
238	1	1
243	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
253	1	1
258	1	1
259	1	1
261	1	1
262	1	1
264	1	1
266	1	1
267	1	1
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
279	1	1
283	1	1
291		unreachable
294	1	1
295	1	1
296	1	1
299		unreachable

---

Cond Coverage for Instance : tb.dut.u_packer

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 7'(OutW))))
             ----------1----------

-1-	Status	Tests
0	Unreachable	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 7'(OutW))))
             ---------------1--------------

-1-	Status	Tests
0	Unreachable	T13,T26,T27
1	Not Covered

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T9,T13,T14
1	1	Covered	T1,T4,T5

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T13,T23
1	1	Covered	T1,T4,T5

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_packer

	Line No.	Total	Covered	Percent
Branches		27	26	96.30
TERNARY	170	2	2	100.00
TERNARY	171	2	2	100.00
TERNARY	283	1	1	100.00
IF	159	2	2	100.00
CASE	185	4	4	100.00
IF	214	3	3	100.00
IF	235	2	2	100.00
CASE	248	4	4	100.00
CASE	80	4	3	75.00
IF	90	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	171	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	159	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests	Exclude Annotation
2'b00	Covered	T1,T2,T3
2'b01	Covered	T1,T4,T5
2'b10	Covered	T1,T4,T5
2'b11	Covered	T13,T26,T27
default	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	217	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	248	case (flush_st)
-2-:	250	if (flush_i)
-3-:	258	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
FlushIdle	1	-	Covered	T1,T4,T5
FlushIdle	0	-	Covered	T1,T2,T3
FlushSend	-	1	Covered	T1,T4,T5
FlushSend	-	0	Covered	T1,T4,T5
default	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	80	case ({ack_in, ack_out})
-2-:	82	((int'(pos_q) <= OutW)) ? 
-3-:	84	((int'(pos_with_input) <= OutW)) ? 

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
2'b00	-	-	Covered	T1,T2,T3
2'b01	1	-	Covered	T1,T4,T5
2'b01	0	-	Unreachable	T1,T4,T5
2'b10	-	-	Covered	T1,T4,T5
2'b11	-	1	Not Covered
2'b11	-	0	Unreachable	T13,T26,T27
default	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	397277403	139	0	492
DataOStableWhenPending_A	397277403	261	0	492
ExFlushValid_M	397277403	17767	0	0
ExcessiveDataStored_A	397277403	3	0	0
ExcessiveMaskStored_A	397277403	3	0	0
FlushFollowedByDone_A	397277403	17767	0	492
ValidIDeassertedOnFlush_M	397277403	28610	0	0
ValidOAssertedForStoredDataGTEOutW_A	397277403	7495919	0	0
ValidOPairedWidthReadyI_A	397277403	261	0	0
gen_mask_assert.ContiguousOnesMask_M	397277403	9785373	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	139	0	492
T9	845998	2	0	1
T13	0	7	0	0
T14	0	2	0	0
T20	0	24	0	0
T22	744470	0	0	1
T24	9590	0	0	1
T26	0	25	0	0
T27	0	10	0	0
T28	0	9	0	0
T29	0	41	0	0
T30	0	19	0	0
T31	231907	0	0	1
T32	254485	0	0	1
T33	123341	0	0	1
T34	817	0	0	1
T35	156525	0	0	1
T36	1232	0	0	1
T37	1221	0	0	1

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	261	0	492
T9	845998	8	0	1
T13	0	52	0	0
T14	0	8	0	0
T20	0	31	0	0
T22	744470	0	0	1
T23	0	2	0	0
T24	9590	0	0	1
T26	0	36	0	0
T27	0	12	0	0
T28	0	21	0	0
T29	0	57	0	0
T30	0	34	0	0
T31	231907	0	0	1
T32	254485	0	0	1
T33	123341	0	0	1
T34	817	0	0	1
T35	156525	0	0	1
T36	1232	0	0	1
T37	1221	0	0	1

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	17767	0	0
T1	83190	2	0	0
T2	743	0	0	0
T3	1242	0	0	0
T4	6847	2	0	0
T5	221190	11	0	0
T6	626631	180	0	0
T7	892487	20	0	0
T8	0	15	0	0
T9	0	116	0	0
T10	373060	386	0	0
T16	1183	0	0	0
T17	122357	3	0	0
T24	0	3	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	3	0	0
T13	159601	1	0	0
T25	168238	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T38	734744	0	0	0
T39	1214	0	0	0
T40	599271	0	0	0
T41	260349	0	0	0
T42	324317	0	0	0
T43	15208	0	0	0
T44	41861	0	0	0
T45	159917	0	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	3	0	0
T13	159601	1	0	0
T25	168238	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T38	734744	0	0	0
T39	1214	0	0	0
T40	599271	0	0	0
T41	260349	0	0	0
T42	324317	0	0	0
T43	15208	0	0	0
T44	41861	0	0	0
T45	159917	0	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	17767	0	492
T1	83190	2	0	1
T2	743	0	0	1
T3	1242	0	0	1
T4	6847	2	0	1
T5	221190	11	0	1
T6	626631	180	0	1
T7	892487	20	0	1
T8	0	15	0	0
T9	0	116	0	0
T10	373060	386	0	1
T16	1183	0	0	1
T17	122357	3	0	1
T24	0	3	0	0

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	28610	0	0
T1	83190	4	0	0
T2	743	0	0	0
T3	1242	0	0	0
T4	6847	4	0	0
T5	221190	20	0	0
T6	626631	310	0	0
T7	892487	33	0	0
T8	0	23	0	0
T9	0	209	0	0
T10	373060	674	0	0
T16	1183	0	0	0
T17	122357	6	0	0
T24	0	5	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	7495919	0	0
T1	83190	1984	0	0
T2	743	0	0	0
T3	1242	0	0	0
T4	6847	891	0	0
T5	221190	6755	0	0
T6	626631	106579	0	0
T7	892487	8471	0	0
T8	0	5506	0	0
T9	0	55680	0	0
T10	373060	212416	0	0
T16	1183	0	0	0
T17	122357	4544	0	0
T24	0	112	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	261	0	0
T9	845998	8	0	0
T13	0	52	0	0
T14	0	8	0	0
T20	0	31	0	0
T22	744470	0	0	0
T23	0	2	0	0
T24	9590	0	0	0
T26	0	36	0	0
T27	0	12	0	0
T28	0	21	0	0
T29	0	57	0	0
T30	0	34	0	0
T31	231907	0	0	0
T32	254485	0	0	0
T33	123341	0	0	0
T34	817	0	0	0
T35	156525	0	0	0
T36	1232	0	0	0
T37	1221	0	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397277403	9785373	0	0
T1	83190	2760	0	0
T2	743	0	0	0
T3	1242	0	0	0
T4	6847	954	0	0
T5	221190	6786	0	0
T6	626631	134822	0	0
T7	892487	11811	0	0
T8	0	7648	0	0
T9	0	59338	0	0
T10	373060	294667	0	0
T16	1183	0	0	0
T17	122357	6371	0	0
T24	0	165	0	0