Unified Coverage Report :: Module :: prim_sha2

Module : prim_sha2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.96	98.58	95.17		90.00	92.11

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode	99.12	100.00	97.87		100.00	98.59

---

Module Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.12	100.00	97.87		100.00	98.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	98.13	96.42		95.00	95.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.39	100.00	98.18			100.00		u_prim_sha2_512

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pad	93.70	96.12	94.93		90.91	92.86

Line Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
TOTAL		141	139	98.58
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	92	14	14	100.00
ALWAYS	117	4	4	100.00
ALWAYS	123	10	10	100.00
ALWAYS	140	3	3	100.00
ALWAYS	146	19	19	100.00
ALWAYS	174	3	3	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	271	7	7	100.00
ALWAYS	288	3	3	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	298	3	3	100.00
CONT_ASSIGN	303	1	1	100.00
ALWAYS	306	3	3	100.00
CONT_ASSIGN	312	1	1	100.00
ALWAYS	315	3	3	100.00
ALWAYS	320	26	26	100.00
ALWAYS	371	3	3	100.00
ALWAYS	385	3	3	100.00
ALWAYS	392	3	3	100.00
CONT_ASSIGN	396	1	1	100.00
ALWAYS	399	23	21	91.30
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	483	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
78	1	1
80	1	1
92	1	1
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
100	1	1
101	1	1
102	1	1
104	1	1
106	1	1
107	1	1
			==> MISSING_ELSE
109	1	1
111	1	1
			MISSING_ELSE
117	2	2
118	2	2
			==> MISSING_ELSE
123	1	1
124	1	1
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
132	1	1
133	1	1
			==> MISSING_ELSE
			MISSING_ELSE
140	2	2
141	1	1
146	1	1
147	1	1
148	1	1
149	1	1
150	1	1
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			==> MISSING_ELSE
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
165	1	1
166	1	1
167	1	1
			MISSING_ELSE
174	2	2
175	1	1
179	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
279	1	1
281	1	1
			MISSING_ELSE
288	2	2
289	1	1
293	1	1
298	2	2
299	1	1
303	1	1
306	2	2
307	1	1
312	1	1
315	2	2
316	1	1
320	1	1
321	1	1
322	1	1
324	1	1
326	2	2
327	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
338	1	1
340	1	1
341	1	1
346	1	1
347	1	1
349	1	1
350	1	1
351	1	1
353	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
			MISSING_ELSE
371	2	2
372	1	1
385	2	2
386	1	1
392	2	2
393	1	1
396	1	1
399	1	1
400	1	1
401	1	1
402	1	1
403	1	1
405	1	1
407	1	1
408	1	1
409	1	1
411	1	1
416	1	1
417	1	1
420	1	1
421	1	1
422	1	1
424	1	1
429	1	1
430	1	1
431	0	1
432	0	1
434	1	1
443	2	2
			MISSING_ELSE
449	1	1
453	1	1
480	1	1
483	1	1

---

Cond Coverage for Module : prim_sha2

	Total	Covered	Percent
Conditions	145	138	95.17
Logical	145	138	95.17
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5

 LINE       80
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? SHA2_None : digest_mode_flag_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       80
 SUB-EXPRESSION (hash_done_o ? SHA2_None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       95
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       102
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T8

 LINE       106
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T5,T6
1	0	Covered	T4,T5,T10

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T5,T10

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T10
1	Covered	T1,T5,T6

 LINE       129
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T8

 LINE       132
 EXPRESSION ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T4,T5,T10
1	0	Covered	T1,T5,T6

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T10
1	Covered	T1,T5,T6

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T5,T10

 LINE       151
 EXPRESSION (digest_mode_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T8

 LINE       153
 EXPRESSION (digest_mode_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T5,T10

 LINE       155
 EXPRESSION (digest_mode_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T5,T6

 LINE       163
 EXPRESSION (digest_we_i[i] ? digest_i[i] : gen_multimode.digest_q[i])
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       272
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       293
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       335
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       346
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       396
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5

 LINE       396
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       407
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       417
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T5
1	-	Covered	T6,T7,T8

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T8

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T5,T6
1	0	Covered	T4,T5,T10

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T5,T10

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T10
1	Covered	T1,T5,T6

 LINE       430
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Not Covered

 LINE       443
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       449
 EXPRESSION 
 Number  Term
      1  update_digest && 
      2  (fifo_st_q == FifoIdle) && 
      3  (((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))))

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T10,T6
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T4,T5,T10

 LINE       449
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || 
      2  ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0))
                 ----------------1---------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       449
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       449
 SUB-EXPRESSION (message_length_i[8:0] == '0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))
                 ------------------------1-----------------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       449
 SUB-EXPRESSION (message_length_i[9:0] == '0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       453
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T6,T7,T8

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       453
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       453
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T4,T5,T10

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T10

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       453
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       480
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T5
0	1	0	Covered	T1,T4,T5
1	0	0	Covered	T1,T4,T5

 LINE       483
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_sha2

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	320	Covered	T1,T2,T3
FifoLoadFromFifo	326	Covered	T1,T4,T5
FifoWait	336	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	326	Covered	T1,T4,T5
FifoLoadFromFifo->FifoIdle	320	Covered	T11,T12,T19
FifoLoadFromFifo->FifoWait	336	Covered	T1,T4,T5
FifoWait->FifoIdle	320	Covered	T1,T4,T5
FifoWait->FifoLoadFromFifo	351	Covered	T1,T4,T5

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	409	Covered	T1,T4,T5
ShaIdle	411	Covered	T1,T2,T3
ShaUpdateDigest	422	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests
ShaCompress->ShaIdle	443	Covered	T6,T11,T12
ShaCompress->ShaUpdateDigest	422	Covered	T1,T4,T5
ShaIdle->ShaCompress	409	Covered	T1,T4,T5
ShaUpdateDigest->ShaCompress	432	Not Covered
ShaUpdateDigest->ShaIdle	434	Covered	T1,T4,T5

---

Branch Coverage for Module : prim_sha2

	Line No.	Total	Covered	Percent
Branches		76	70	92.11
TERNARY	80	3	3	100.00
TERNARY	293	3	3	100.00
TERNARY	453	3	3	100.00
IF	272	4	4	100.00
IF	288	2	2	100.00
IF	298	2	2	100.00
IF	306	2	2	100.00
IF	315	2	2	100.00
CASE	324	9	8	88.89
IF	362	3	3	100.00
IF	371	2	2	100.00
IF	385	2	2	100.00
IF	392	2	2	100.00
CASE	405	8	6	75.00
IF	443	2	2	100.00
IF	93	8	7	87.50
IF	117	3	2	66.67
IF	124	6	5	83.33
IF	140	2	2	100.00
IF	147	6	6	100.00
IF	174	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	(hash_go) ? 
-2-:	80	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	(((~sha_en_i) || hash_go)) ? 
-2-:	293	(update_w_from_fifo) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	453	((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? 
-2-:	453	((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	272	if (((!sha_en_i) || hash_go))
-2-:	274	if (run_hash)
-3-:	275	if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T4,T5
0	1	0	Covered	T1,T4,T5
0	0	-	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	298	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	306	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	case (fifo_st_q)
-2-:	326	if (hash_go)
-3-:	331	if ((!shaf_rvalid))
-4-:	335	if ((w_index_q == 4'd15))
-5-:	346	if ((msg_feed_complete && one_chunk_done))
-6-:	350	if (one_chunk_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
FifoIdle	1	-	-	-	-	Covered	T1,T4,T5
FifoIdle	0	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	Covered	T1,T4,T5
FifoLoadFromFifo	-	0	1	-	-	Covered	T1,T4,T5
FifoLoadFromFifo	-	0	0	-	-	Covered	T1,T4,T5
FifoWait	-	-	-	1	-	Covered	T1,T4,T5
FifoWait	-	-	-	0	1	Covered	T1,T4,T5
FifoWait	-	-	-	0	0	Covered	T1,T4,T5
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	362	if ((!sha_en_i))
-2-:	365	if (hash_go)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	371	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	385	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	405	case (sha_st_q)
-2-:	407	if ((fifo_st_q == FifoWait))
-3-:	417	if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))))
-4-:	421	if (one_chunk_done)
-5-:	430	if ((fifo_st_q == FifoWait))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
ShaIdle	1	-	-	-	Covered	T1,T4,T5
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T1,T4,T5
ShaCompress	-	0	1	-	Covered	T1,T4,T5
ShaCompress	-	0	0	-	Covered	T1,T4,T5
ShaUpdateDigest	-	-	-	1	Not Covered
ShaUpdateDigest	-	-	-	0	Covered	T1,T4,T5
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	443	if (((!sha_en_i) || hash_go))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	93	if (wipe_secret_i)
-2-:	95	if (((!sha_en_i) || hash_go))
-3-:	97	if (((!run_hash) && update_w_from_fifo))
-4-:	101	if (calculate_next_w)
-5-:	102	if ((digest_mode_flag_q == SHA2_256))
-6-:	106	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))
-7-:	109	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
1	-	-	-	-	-	-	Covered	T6,T22,T25
0	1	-	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	-	Covered	T1,T4,T5
0	0	0	1	1	-	-	Covered	T6,T7,T8
0	0	0	1	0	1	-	Covered	T1,T4,T5
0	0	0	1	0	0	-	Not Covered
0	0	0	0	-	-	1	Covered	T1,T4,T5
0	0	0	0	-	-	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	117	if ((!rst_ni))
-2-:	118	if (MultimodeEn)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

	LineNo.	Expression
-1-:	124	if (wipe_secret_i)
-2-:	126	if (init_hash)
-3-:	128	if (run_hash)
-4-:	129	if ((digest_mode_flag_q == SHA2_256))
-5-:	132	if (((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T6,T22,T25
0	1	-	-	-	Covered	T1,T4,T5
0	0	1	1	-	Covered	T6,T7,T8
0	0	1	0	1	Covered	T1,T4,T5
0	0	1	0	0	Not Covered
0	0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	147	if (wipe_secret_i)
-2-:	149	if (hash_start_i)
-3-:	159	if (clear_digest)
-4-:	161	if ((!sha_en_i))
-5-:	165	if (update_digest)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T6,T22,T25
0	1	-	-	-	Covered	T1,T4,T5
0	0	1	-	-	Covered	T4,T5,T6
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T4,T5
0	0	0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	174	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

	Line No.	Total	Covered	Percent
TOTAL		139	139	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	92	14	14	100.00
ALWAYS	117	4	4	100.00
ALWAYS	123	10	10	100.00
ALWAYS	140	3	3	100.00
ALWAYS	146	19	19	100.00
ALWAYS	174	3	3	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	271	7	7	100.00
ALWAYS	288	3	3	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	298	3	3	100.00
CONT_ASSIGN	303	1	1	100.00
ALWAYS	306	3	3	100.00
CONT_ASSIGN	312	1	1	100.00
ALWAYS	315	3	3	100.00
ALWAYS	320	26	26	100.00
ALWAYS	371	3	3	100.00
ALWAYS	385	3	3	100.00
ALWAYS	392	3	3	100.00
CONT_ASSIGN	396	1	1	100.00
ALWAYS	399	21	21	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	453	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	483	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
78	1	1
80	1	1
92	1	1
93	1	1
94	1	1
95	1	1
96	1	1
97	1	1
100	1	1
101	1	1
102	1	1
104	1	1
106	1	1
107	1	1
			==> MISSING_ELSE
109	1	1
111	1	1
			MISSING_ELSE
117	2	2
118	2	2
			==> MISSING_ELSE
123	1	1
124	1	1
125	1	1
126	1	1
127	1	1
128	1	1
129	1	1
130	1	1
132	1	1
133	1	1
			==> MISSING_ELSE
			MISSING_ELSE
140	2	2
141	1	1
146	1	1
147	1	1
148	1	1
149	1	1
150	1	1
151	1	1
152	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			==> MISSING_ELSE
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
165	1	1
166	1	1
167	1	1
			MISSING_ELSE
174	2	2
175	1	1
179	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
279	1	1
281	1	1
			MISSING_ELSE
288	2	2
289	1	1
293	1	1
298	2	2
299	1	1
303	1	1
306	2	2
307	1	1
312	1	1
315	2	2
316	1	1
320	1	1
321	1	1
322	1	1
324	1	1
326	2	2
327	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
338	1	1
340	1	1
341	1	1
346	1	1
347	1	1
349	1	1
350	1	1
351	1	1
353	1	1
			Exclude Annotation: VC_COV_UNR
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
			MISSING_ELSE
371	2	2
372	1	1
385	2	2
386	1	1
392	2	2
393	1	1
396	1	1
399	1	1
400	1	1
401	1	1
402	1	1
403	1	1
405	1	1
407	1	1
408	1	1
409	1	1
411	1	1
416	1	1
417	1	1
420	1	1
421	1	1
422	1	1
424	1	1
429	1	1
430	1	1
431		excluded
			Exclude Annotation: VC_COV_UNR
432		excluded
			Exclude Annotation: VC_COV_UNR
434	1	1
			Exclude Annotation: VC_COV_UNR
443	2	2
			MISSING_ELSE
449	1	1
453	1	1
480	1	1
483	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

	Total	Covered	Percent
Conditions	141	138	97.87
Logical	141	138	97.87
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (hash_start_i | hash_continue_i)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5

 LINE       80
 EXPRESSION (hash_go ? digest_mode_i : (hash_done_o ? SHA2_None : digest_mode_flag_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       80
 SUB-EXPRESSION (hash_done_o ? SHA2_None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       95
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (((!run_hash)) && update_w_from_fifo)
             ------1------    ---------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       102
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T8

 LINE       106
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		VC_COV_UNR
0	1	Covered	T1,T5,T6
1	0	Covered	T4,T5,T10

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T5,T10

 LINE       106
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T10
1	Covered	T1,T5,T6

 LINE       129
 EXPRESSION (digest_mode_flag_q == SHA2_256)
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T8

 LINE       132
 EXPRESSION ((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T4,T5,T10
1	0	Covered	T1,T5,T6

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T10
1	Covered	T1,T5,T6

 LINE       132
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T5,T10

 LINE       151
 EXPRESSION (digest_mode_i == SHA2_256)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T8

 LINE       153
 EXPRESSION (digest_mode_i == SHA2_384)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T5,T10

 LINE       155
 EXPRESSION (digest_mode_i == SHA2_512)
            -------------1-------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T5,T6

 LINE       163
 EXPRESSION (digest_we_i[i] ? digest_i[i] : gen_multimode.digest_q[i])
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       272
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       293
 EXPRESSION ((((~sha_en_i)) || hash_go) ? '0 : (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q))
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (((~sha_en_i)) || hash_go)
                 ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (update_w_from_fifo ? ((w_index_q + 1)) : w_index_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       335
 EXPRESSION (w_index_q == 4'd15)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       346
 EXPRESSION (msg_feed_complete && one_chunk_done)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       396
 EXPRESSION (hash_start_i | (((~sha_en_i)) & sha_en_q))
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5

 LINE       396
 SUB-EXPRESSION (((~sha_en_i)) & sha_en_q)
                 ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       407
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       417
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30)) || 
      2  (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q < 7'h30))
                 ---------------------------1--------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T5
1	-	Covered	T6,T7,T8

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T8

 LINE       417
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))
                 -----------------------------------1----------------------------------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       417
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T5,T6
1	0	Covered	T4,T5,T10

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T5,T10

 LINE       417
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T10
1	Covered	T1,T5,T6

 LINE       430
 EXPRESSION (fifo_st_q == FifoWait)
            -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T4,T5
1	Excluded		VC_COV_UNR

 LINE       443
 EXPRESSION (((!sha_en_i)) || hash_go)
             ------1------    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       449
 EXPRESSION 
 Number  Term
      1  update_digest && 
      2  (fifo_st_q == FifoIdle) && 
      3  (((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))))

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T10,T6
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T4,T5,T10

 LINE       449
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION 
 Number  Term
      1  ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0)) || 
      2  ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0)))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) && (message_length_i[8:0] == '0))
                 ----------------1---------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       449
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       449
 SUB-EXPRESSION (message_length_i[8:0] == '0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION ((digest_mode_flag_q inside {SHA2_384, SHA2_512}) && (message_length_i[9:0] == '0))
                 ------------------------1-----------------------    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       449
 SUB-EXPRESSION (message_length_i[9:0] == '0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       453
 EXPRESSION 
 Number  Term
      1  (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63)) ? 1'b1 : ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn))) && (round_q == 7'd63))
                 ---------------------------1--------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_256) || ((~MultimodeEn)))
                 ----------------1---------------    --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T6,T7,T8

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_256)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T8

 LINE       453
 SUB-EXPRESSION (round_q == 7'd63)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       453
 SUB-EXPRESSION ((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79)) ? 1'b1 : 1'b0)
                 -----------------------------------------------1----------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       453
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))
                 -----------------------------------1----------------------------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       453
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T4,T5,T10

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T10

 LINE       453
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       453
 SUB-EXPRESSION (round_q == 7'd79)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       480
 EXPRESSION (init_hash | run_hash | update_digest)
             ----1----   ----2---   ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T5
0	1	0	Covered	T1,T4,T5
1	0	0	Covered	T1,T4,T5

 LINE       483
 EXPRESSION ((fifo_st_q == FifoIdle) && (sha_st_q == ShaIdle) && ((!hash_go)))
             -----------1-----------    ----------2----------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (fifo_st_q == FifoIdle)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       483
 SUB-EXPRESSION (sha_st_q == ShaIdle)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

Summary for FSM :: fifo_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	5	5	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fifo_st_q

---

states	Line No.	Covered	Tests
FifoIdle	320	Covered	T1,T2,T3
FifoLoadFromFifo	326	Covered	T1,T4,T5
FifoWait	336	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests
FifoIdle->FifoLoadFromFifo	326	Covered	T1,T4,T5
FifoLoadFromFifo->FifoIdle	320	Covered	T11,T12,T19
FifoLoadFromFifo->FifoWait	336	Covered	T1,T4,T5
FifoWait->FifoIdle	320	Covered	T1,T4,T5
FifoWait->FifoLoadFromFifo	351	Covered	T1,T4,T5

Summary for FSM :: sha_st_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: sha_st_q

---

states	Line No.	Covered	Tests
ShaCompress	409	Covered	T1,T4,T5
ShaIdle	411	Covered	T1,T2,T3
ShaUpdateDigest	422	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
ShaCompress->ShaIdle	443	Covered	T6,T11,T12
ShaCompress->ShaUpdateDigest	422	Covered	T1,T4,T5
ShaIdle->ShaCompress	409	Covered	T1,T4,T5
ShaUpdateDigest->ShaCompress	432	Excluded		VC_COV_UNR
ShaUpdateDigest->ShaIdle	434	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode

	Line No.	Total	Covered	Percent
Branches		71	70	98.59
TERNARY	80	3	3	100.00
TERNARY	293	3	3	100.00
TERNARY	453	3	3	100.00
IF	272	4	4	100.00
IF	288	2	2	100.00
IF	298	2	2	100.00
IF	306	2	2	100.00
IF	315	2	2	100.00
CASE	324	8	8	100.00
IF	362	3	3	100.00
IF	371	2	2	100.00
IF	385	2	2	100.00
IF	392	2	2	100.00
CASE	405	6	6	100.00
IF	443	2	2	100.00
IF	93	7	7	100.00
IF	117	2	2	100.00
IF	124	6	5	83.33
IF	140	2	2	100.00
IF	147	6	6	100.00
IF	174	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	(hash_go) ? 
-2-:	80	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	(((~sha_en_i) || hash_go)) ? 
-2-:	293	(update_w_from_fifo) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	453	((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q == 7'd63))) ? 
-2-:	453	((((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q == 7'd79))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T8
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	272	if (((!sha_en_i) || hash_go))
-2-:	274	if (run_hash)
-3-:	275	if ((((round_q[(RndWidth256 - 1):0] == 6'((unsigned'((prim_sha2_pkg::NumRound256 - 1))))) && ((digest_mode_flag_q == SHA2_256) || (!MultimodeEn))) || ((round_q == 7'((unsigned'((prim_sha2_pkg::NumRound512 - 1))))) && ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	1	Covered	T1,T4,T5
0	1	0	Covered	T1,T4,T5
0	0	-	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	298	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	306	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	324	case (fifo_st_q)
-2-:	326	if (hash_go)
-3-:	331	if ((!shaf_rvalid))
-4-:	335	if ((w_index_q == 4'd15))
-5-:	346	if ((msg_feed_complete && one_chunk_done))
-6-:	350	if (one_chunk_done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests	Exclude Annotation
FifoIdle	1	-	-	-	-	Covered	T1,T4,T5
FifoIdle	0	-	-	-	-	Covered	T1,T2,T3
FifoLoadFromFifo	-	1	-	-	-	Covered	T1,T4,T5
FifoLoadFromFifo	-	0	1	-	-	Covered	T1,T4,T5
FifoLoadFromFifo	-	0	0	-	-	Covered	T1,T4,T5
FifoWait	-	-	-	1	-	Covered	T1,T4,T5
FifoWait	-	-	-	0	1	Covered	T1,T4,T5
FifoWait	-	-	-	0	0	Covered	T1,T4,T5
default	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	362	if ((!sha_en_i))
-2-:	365	if (hash_go)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	371	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	385	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	392	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	405	case (sha_st_q)
-2-:	407	if ((fifo_st_q == FifoWait))
-3-:	417	if (((((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)) && (round_q < 7'h30)) || (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) && (round_q < 7'h40))))
-4-:	421	if (one_chunk_done)
-5-:	430	if ((fifo_st_q == FifoWait))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
ShaIdle	1	-	-	-	Covered	T1,T4,T5
ShaIdle	0	-	-	-	Covered	T1,T2,T3
ShaCompress	-	1	-	-	Covered	T1,T4,T5
ShaCompress	-	0	1	-	Covered	T1,T4,T5
ShaCompress	-	0	0	-	Covered	T1,T4,T5
ShaUpdateDigest	-	-	-	1	Excluded		VC_COV_UNR
ShaUpdateDigest	-	-	-	0	Covered	T1,T4,T5
default	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	443	if (((!sha_en_i) || hash_go))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	93	if (wipe_secret_i)
-2-:	95	if (((!sha_en_i) || hash_go))
-3-:	97	if (((!run_hash) && update_w_from_fifo))
-4-:	101	if (calculate_next_w)
-5-:	102	if ((digest_mode_flag_q == SHA2_256))
-6-:	106	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))
-7-:	109	if (run_hash)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests	Exclude Annotation
1	-	-	-	-	-	-	Covered	T6,T22,T25
0	1	-	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	-	Covered	T1,T4,T5
0	0	0	1	1	-	-	Covered	T6,T7,T8
0	0	0	1	0	1	-	Covered	T1,T4,T5
0	0	0	1	0	0	-	Excluded		VC_COV_UNR
0	0	0	0	-	-	1	Covered	T1,T4,T5
0	0	0	0	-	-	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	117	if ((!rst_ni))
-2-:	118	if (MultimodeEn)

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	124	if (wipe_secret_i)
-2-:	126	if (init_hash)
-3-:	128	if (run_hash)
-4-:	129	if ((digest_mode_flag_q == SHA2_256))
-5-:	132	if (((digest_mode_flag_q == SHA2_512) || (digest_mode_flag_q == SHA2_384)))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T6,T22,T25
0	1	-	-	-	Covered	T1,T4,T5
0	0	1	1	-	Covered	T6,T7,T8
0	0	1	0	1	Covered	T1,T4,T5
0	0	1	0	0	Not Covered
0	0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	147	if (wipe_secret_i)
-2-:	149	if (hash_start_i)
-3-:	159	if (clear_digest)
-4-:	161	if ((!sha_en_i))
-5-:	165	if (update_digest)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T6,T22,T25
0	1	-	-	-	Covered	T1,T4,T5
0	0	1	-	-	Covered	T4,T5,T6
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T4,T5
0	0	0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	174	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3