Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43146925	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

41180327

1

T1

455818

T2

37905

T3

967520

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	40092405	1			T1	403886		T2	42881		T3	921193
values[0x0]	20717784	1			T1	217544		T2	19271		T3	493716
values[0x1]	23517063	1			T1	258922		T2	22938		T3	542926

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33189802	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

51137450

1

T1

563498

T2

48733

T3

119136

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	257006	1			T1	3568		T2	331		T3	7481
valid_sources[0x01]	290424	1			T1	1789		T2	351		T3	7649
valid_sources[0x02]	299198	1			T1	3777		T2	334		T3	7648
valid_sources[0x03]	253521	1			T1	2637		T2	349		T3	7691
valid_sources[0x04]	253447	1			T1	3283		T2	304		T3	7673
valid_sources[0x05]	261173	1			T1	1753		T2	342		T3	7505
valid_sources[0x06]	255204	1			T1	3037		T2	327		T3	7722
valid_sources[0x07]	254098	1			T1	1425		T2	345		T3	7555
valid_sources[0x08]	255662	1			T1	2411		T2	269		T3	7704
valid_sources[0x09]	253136	1			T1	1867		T2	326		T3	7727
valid_sources[0x0a]	332656	1			T1	5169		T2	295		T3	7636
valid_sources[0x0b]	1023058	1			T1	2020		T2	245		T3	7778
valid_sources[0x0c]	256207	1			T1	4185		T2	273		T3	7611
valid_sources[0x0d]	274469	1			T1	3028		T2	366		T3	7476
valid_sources[0x0e]	283343	1			T1	31005		T2	348		T3	7629
valid_sources[0x0f]	250304	1			T1	1947		T2	286		T3	7580
valid_sources[0x10]	370990	1			T1	4795		T2	344		T3	7723
valid_sources[0x11]	404003	1			T1	3219		T2	379		T3	7644
valid_sources[0x12]	260061	1			T1	5482		T2	370		T3	7657
valid_sources[0x13]	951100	1			T1	3059		T2	373		T3	7694
valid_sources[0x14]	256028	1			T1	2002		T2	353		T3	7690
valid_sources[0x15]	255076	1			T1	4567		T2	291		T3	7737
valid_sources[0x16]	257471	1			T1	3888		T2	403		T3	7509
valid_sources[0x17]	257233	1			T1	3469		T2	302		T3	7653
valid_sources[0x18]	366751	1			T1	3174		T2	281		T3	7483
valid_sources[0x19]	253418	1			T1	1907		T2	335		T3	7718
valid_sources[0x1a]	254313	1			T1	3401		T2	295		T3	7716
valid_sources[0x1b]	258204	1			T1	4931		T2	329		T3	7834
valid_sources[0x1c]	324308	1			T1	2292		T2	401		T3	7534
valid_sources[0x1d]	255670	1			T1	3111		T2	276		T3	7591
valid_sources[0x1e]	310667	1			T1	2508		T2	325		T3	7558
valid_sources[0x1f]	252047	1			T1	2727		T2	350		T3	7863
valid_sources[0x20]	253696	1			T1	2912		T2	364		T3	7401
valid_sources[0x21]	368811	1			T1	2784		T2	356		T3	7597
valid_sources[0x22]	257741	1			T1	4468		T2	298		T3	7765
valid_sources[0x23]	298152	1			T1	4187		T2	339		T3	7757
valid_sources[0x24]	254812	1			T1	2556		T2	349		T3	7748
valid_sources[0x25]	258678	1			T1	3567		T2	365		T3	7754
valid_sources[0x26]	255111	1			T1	2830		T2	311		T3	7825
valid_sources[0x27]	251581	1			T1	3072		T2	350		T3	7744
valid_sources[0x28]	256720	1			T1	2630		T2	385		T3	7579
valid_sources[0x29]	261481	1			T1	3338		T2	382		T3	7701
valid_sources[0x2a]	1275816	1			T1	2547		T2	329		T3	7728
valid_sources[0x2b]	256777	1			T1	3458		T2	324		T3	7588
valid_sources[0x2c]	309281	1			T1	4054		T2	286		T3	7605
valid_sources[0x2d]	256736	1			T1	3923		T2	261		T3	7576
valid_sources[0x2e]	268635	1			T1	3561		T2	306		T3	7440
valid_sources[0x2f]	253214	1			T1	3099		T2	303		T3	7623
valid_sources[0x30]	256202	1			T1	4493		T2	369		T3	7697
valid_sources[0x31]	256322	1			T1	2615		T2	434		T3	7795
valid_sources[0x32]	2046379	1			T1	4509		T2	340		T3	7767
valid_sources[0x33]	254989	1			T1	2352		T2	369		T3	7725
valid_sources[0x34]	292407	1			T1	3218		T2	252		T3	7863
valid_sources[0x35]	280224	1			T1	2226		T2	340		T3	7625
valid_sources[0x36]	257140	1			T1	3505		T2	405		T3	7590
valid_sources[0x37]	254486	1			T1	3703		T2	336		T3	7505
valid_sources[0x38]	253473	1			T1	3079		T2	340		T3	7648
valid_sources[0x39]	257404	1			T1	4517		T2	370		T3	7528
valid_sources[0x3a]	443202	1			T1	3224		T2	333		T3	7665
valid_sources[0x3b]	294246	1			T1	1331		T2	295		T3	7867
valid_sources[0x3c]	268773	1			T1	5890		T2	310		T3	7630
valid_sources[0x3d]	256076	1			T1	3022		T2	270		T3	7607
valid_sources[0x3e]	260919	1			T1	3006		T2	318		T3	7757
valid_sources[0x3f]	250313	1			T1	1306		T2	348		T3	7423
valid_sources[0x40]	252721	1			T1	1587		T2	313		T3	7640
valid_sources[0x41]	266053	1			T1	3962		T2	363		T3	7754
valid_sources[0x42]	275142	1			T1	2586		T2	260		T3	7852
valid_sources[0x43]	254629	1			T1	2927		T2	370		T3	7924
valid_sources[0x44]	274777	1			T1	2229		T2	302		T3	7548
valid_sources[0x45]	255581	1			T1	4312		T2	318		T3	7582
valid_sources[0x46]	255243	1			T1	2396		T2	318		T3	7791
valid_sources[0x47]	254775	1			T1	3429		T2	298		T3	7697
valid_sources[0x48]	260694	1			T1	3169		T2	304		T3	7771
valid_sources[0x49]	255798	1			T1	2982		T2	296		T3	7781
valid_sources[0x4a]	281845	1			T1	4510		T2	341		T3	7692
valid_sources[0x4b]	258127	1			T1	3670		T2	395		T3	7644
valid_sources[0x4c]	259502	1			T1	2251		T2	414		T3	7573
valid_sources[0x4d]	324964	1			T1	4628		T2	310		T3	7717
valid_sources[0x4e]	254166	1			T1	5786		T2	361		T3	7619
valid_sources[0x4f]	258097	1			T1	3243		T2	319		T3	7692
valid_sources[0x50]	263791	1			T1	3208		T2	365		T3	7564
valid_sources[0x51]	303895	1			T1	3284		T2	373		T3	7684
valid_sources[0x52]	254941	1			T1	3244		T2	404		T3	7747
valid_sources[0x53]	253295	1			T1	3035		T2	337		T3	7690
valid_sources[0x54]	256243	1			T1	3145		T2	415		T3	7595
valid_sources[0x55]	254561	1			T1	2912		T2	346		T3	7665
valid_sources[0x56]	251822	1			T1	1935		T2	303		T3	7638
valid_sources[0x57]	341033	1			T1	4006		T2	331		T3	7777
valid_sources[0x58]	264893	1			T1	2021		T2	284		T3	7898
valid_sources[0x59]	264283	1			T1	4486		T2	386		T3	7599
valid_sources[0x5a]	256186	1			T1	1390		T2	368		T3	7449
valid_sources[0x5b]	257567	1			T1	2846		T2	286		T3	7576
valid_sources[0x5c]	254329	1			T1	3070		T2	339		T3	7638
valid_sources[0x5d]	250207	1			T1	1997		T2	356		T3	7706
valid_sources[0x5e]	258298	1			T1	4815		T2	293		T3	7445
valid_sources[0x5f]	257835	1			T1	1736		T2	317		T3	7630
valid_sources[0x60]	2084843	1			T1	3218		T2	412		T3	7833
valid_sources[0x61]	252918	1			T1	2238		T2	330		T3	7711
valid_sources[0x62]	256852	1			T1	3420		T2	297		T3	7409
valid_sources[0x63]	709725	1			T1	3659		T2	390		T3	7558
valid_sources[0x64]	257792	1			T1	3763		T2	377		T3	7590
valid_sources[0x65]	498079	1			T1	2636		T2	359		T3	7497
valid_sources[0x66]	256530	1			T1	3717		T2	335		T3	7614
valid_sources[0x67]	252252	1			T1	2749		T2	363		T3	7413
valid_sources[0x68]	300232	1			T1	3179		T2	377		T3	7605
valid_sources[0x69]	387724	1			T1	3317		T2	289		T3	7729
valid_sources[0x6a]	258898	1			T1	7132		T2	321		T3	7740
valid_sources[0x6b]	252052	1			T1	2649		T2	318		T3	7622
valid_sources[0x6c]	255175	1			T1	3028		T2	408		T3	7629
valid_sources[0x6d]	298265	1			T1	4790		T2	314		T3	7472
valid_sources[0x6e]	251519	1			T1	1298		T2	346		T3	7619
valid_sources[0x6f]	254851	1			T1	3693		T2	355		T3	7644
valid_sources[0x70]	252311	1			T1	1417		T2	358		T3	7597
valid_sources[0x71]	257510	1			T1	3033		T2	339		T3	7652
valid_sources[0x72]	838461	1			T1	3528		T2	249		T3	7731
valid_sources[0x73]	457777	1			T1	1893		T2	323		T3	7616
valid_sources[0x74]	267035	1			T1	5524		T2	364		T3	7428
valid_sources[0x75]	257904	1			T1	5230		T2	303		T3	7395
valid_sources[0x76]	256488	1			T1	3216		T2	295		T3	7679
valid_sources[0x77]	259821	1			T1	4764		T2	318		T3	7507
valid_sources[0x78]	414595	1			T1	3539		T2	337		T3	7634
valid_sources[0x79]	618405	1			T1	1533		T2	425		T3	7715
valid_sources[0x7a]	305796	1			T1	2759		T2	277		T3	7926
valid_sources[0x7b]	276458	1			T1	2896		T2	320		T3	7689
valid_sources[0x7c]	254492	1			T1	4261		T2	294		T3	7665
valid_sources[0x7d]	329570	1			T1	2047		T2	332		T3	7555
valid_sources[0x7e]	326413	1			T1	3454		T2	324		T3	7678
valid_sources[0x7f]	321817	1			T1	3497		T2	349		T3	7718
valid_sources[0x80]	330447	1			T1	2962		T2	293		T3	7684

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19861507

1

T1

205931

T2

21523

T3

461064

values[0x0]

all_enables

biggest_size

11468818

1

T1

132277

T2

9035

T3

273380

values[0x1]

all_enables

biggest_size

9850002

1

T1

117610

T2

7347

T3

233076