Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

47021681

1

T1

719089

T2

47185

T3

990315

full_word

41432108

1

T1

475014

T2

37905

T3

967520

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	88453349	1			T1	119410		T2	85090		T3	195783
auto[TlIntgErrCmd]	139	1			T59	6		T60	4		T61	4
auto[TlIntgErrData]	142	1			T59	11		T60	11		T61	10
auto[TlIntgErrBoth]	159	1			T59	13		T60	5		T61	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41389996

1

T1

502283

T2

42881

T3

921193

auto[1]

47063793

1

T1

691820

T2

42209

T3

103664

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21429529	1			T1	288936		T2	21358		T3	460129
auto[TlIntgErrNone]	partial	auto[1]	25591746	1			T1	430153		T2	25827		T3	530186
auto[TlIntgErrNone]	full_word	auto[0]	19960295	1			T1	213347		T2	21523		T3	461064
auto[TlIntgErrNone]	full_word	auto[1]	21471779	1			T1	261667		T2	16382		T3	506456
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T59	3		T61	2		T120	3
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T59	2		T60	2		T61	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T59	1		T60	1		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T60	1		T126	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T59	6		T60	6		T61	3
auto[TlIntgErrData]	partial	auto[1]	71	1			T59	4		T60	4		T61	7
auto[TlIntgErrData]	full_word	auto[0]	2	1			T128	1		T126	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1			T59	1		T60	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T59	4		T60	2		T61	2
auto[TlIntgErrBoth]	partial	auto[1]	96	1			T59	8		T60	3		T61	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T61	1		T122	1		T127	2
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T59	1		T61	1		T120	3